Radhey Shyam Pandey 7cb1e57544 dt-bindings: dmaengine: xilinx_dma: Add binding for Xilinx MCDMA IP ...

Add devicetree binding for Xilinx AXI Multichannel Direct Memory Access
(AXI MCDMA) IP. The AXI MCDMA provides high-bandwidth direct memory
access between memory and AXI4-Stream target peripherals. The AXI MCDMA
core provides a scatter-gather interface with multiple channel support
with independent configuration.

Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1571763622-29281-4-git-send-email-radhey.shyam.pandey@xilinx.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

2019-11-06 22:37:22 +05:30

..

xilinx_dma.txt

dt-bindings: dmaengine: xilinx_dma: Add binding for Xilinx MCDMA IP

2019-11-06 22:37:22 +05:30

zynqmp_dma.txt

dt-bindings: remove 'interrupt-parent' from bindings

2018-07-25 14:09:39 -06:00