Andreas Färber 92c9e0c780 ARM: dts: zynq: Enable PL clocks for Parallella ...

The Parallella board comes with a U-Boot bootloader that loads one of
two predefined FPGA bitstreams before booting the kernel. Both define an
AXI interface to the on-board Epiphany processor.

Enable clocks FCLK0..FCLK3 for the Programmable Logic by default.

Otherwise accessing, e.g., the ESYSRESET register freezes the board,
as seen with the Epiphany SDK tools e-reset and e-hw-rev, using /dev/mem.

Cc: <stable@vger.kernel.org> # 3.17.x
Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Olof Johansson <olof@lixom.net>

2014-11-08 16:57:44 -08:00

..

bootp

ARM: 8153/1: Enable gcov support on the ARM architecture

2014-09-26 14:39:57 +01:00

compressed

ARM: 8153/1: Enable gcov support on the ARM architecture

2014-09-26 14:39:57 +01:00

dts

ARM: dts: zynq: Enable PL clocks for Parallella

2014-11-08 16:57:44 -08:00

.gitignore

ARM: devicetree: Add .dtb files to arch/arm/boot/.gitignore

2012-01-30 11:47:37 -07:00

install.sh

arm, kbuild: make "make install" not depend on vmlinux

2013-10-02 22:30:35 +02:00

Makefile

arm, kbuild: make "make install" not depend on vmlinux

2013-10-02 22:30:35 +02:00