mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-07-27 16:49:22 -04:00
Pull drm updates from Dave Airlie:
"Highlights:
- xe: add initial CRI platform support
- amdgpu: initial HDMI 2.1 FRL support
- rust: add some new type concepts for device lifetimes
- scheduler: moves to a fair algorithm and lots of cleanups
But it's mostly the usual mountain of changes across the board.
core:
- add docbook for DRM_IOCTL_SYNCOBJ_EVENTFD
- change signature of drm_connector_attach_hdr_output_metadata_property
- dedup counter and timestamp retrieval in vblank code
- parse AMD VSDB v3 in CTA extension blocks
- add P230, Y7, XYYY2101010, T430, XVUY210101010 formats
- don't call drop master on file close if not master
- use drm_printf_indent in atomic / bridge
- fix 32b format descriptions
- docs: fix toctree
- hdmi: add common TMDS character rates
- fix drm_syncobj_find_fence leak
rust:
- introduce Higher-Ranked lifetime types
- replace drvdata with scoped registration data
- add GPUVM immediate mode abstraction for rust GPU drivers
- introduce DeviceContext type state for drm::Device
bridge:
- clarify drm_bridge_get/put
- create drm_get_bridge_by_endpoint and use it
- analogix_dp: add panel probing
- ite-it6211 - use drm audio hdmi helpers
buddy:
- add lockdep annotations
dp:
- add PR and VRR updates
- mst: fix buffer overflows
- add Adaptive Sync SDP decoding support
- fix OOB reads in dp-mst
ttm:
- bump fpfn/lpfn to 64-bit
scheduler:
- change default to fair scheduler
- map runqueue 1:1 with scheduler
dma-buf:
- port selftests to kunit
- convert dma-buf system/heap allocators to module
- add separate DMABUF_HEAPS_SYSTEM_CC_SHARED Kconfig
udmabuf:
- revert hugetlb support
- fix error with CONFIG_DMA_API_DEBUG
dma-fence:
- fix tracepoints lifetime
- remove unused signal on any support
ras:
- add clear error counter netlink command to drm ras
gpusvm:
- reject VMAs with VM_IO or VM_PFNMAP when creating SVM ranges
- use IOVA allocations
pagemap:
- use IOVA allocations
panels:
- update to use ref counts
- add support for CSW PNB601LS1-2, LGD LP116WHA-SPB1
- add support for waveshare panels
- CMN N116BCN-EA1, CMN N140HCA-EEK, IVO M140NWFQ R5,
- IVO, R140NWFW R0, BOE NT140*, BOE NV133FHM-N4F,
- AUO B140*, AUO B133HAN06.6 and AUO B116XTN02.3 eDP panels
- Surface Pro 12 Panel
xe:
- add CRI PCI-IDs
- debugfs add multi-lrc info
- engine init cleanup
- PF fair scheduling auto provisioning
- system controller support for CRI/Xe3p
- PXP state machine fixes
- Reset/wedge/unload corner case fixes
- Wedge path memory allocation fixes
- PAT type cleanups
- Reject unsafe PAT for CPU cached memory
- OA improvements for CRI device memory
- kernel doc syntax in xe headers
- xe_drm.h documentation fixes
- include guard cleanups
- VF CCS memory pool
- i915/xe step unification
- Xe3p GT tuning fixes
- forcewake cleanup in GT and GuC
- admin-only PF mode
- enable hwmon energy attributes for CRI
- enable GT_MI_USER_INTERRUPT
- refactor emit functions
- oa workarounds
- multi_queue: allow QUEUE_TIMESTAMP register
- convert stolen memory to ttm range manager
- use xe2 style blitter as a feature flag
- make drm_driver const
- add/use IRQ page to HW engine definition
- fix oops when display disabled
i915:
- enable PIPEDMC_ERROR interrupt
- more common display code refactoring
- restructure DP/HDMI sink format handling
- eliminate FB usage from lowlevel pinning code
- panel replay bw optimization
- integrate sharpness filter into the scaler
- new fb_pin abstraction for xe/i915 fb transparent handling
- skip inactive MST connectors on HDCP
- start switching to display specific registers
- use polling when irq unavailable
- Adaptive-sync SDP prep
amdgpu:
- use drm_display_info for AMD VSDB data
- Initial HDMI 2.1 FRL support
- Initial DCN 4.2.1 support
- GART fixes for non-4k pages
- GC 11.5.6/SDMA 6.4.0/and other new IPs
- GFX9/DCE6/Hawaii/SDMA4/GART/Userq fixes
- Finish support for using multiple SDMA queues for TTM operations
- SWSMU updates
- GC 12.1 updates
- SMU 15.0.8 updates
- DCN 4.2 updates
- DC type conversion fixes
- Enable DC power module
- Replay/PSR updates
- SMU 13.x updates
- Compute queue quantum MQD updates
- ASPM fix
- Align VKMS with common implementation
- DC analog support fixes
- UVD 3 fixes
- TCC harvesting fixes for SI
- GC 11 APU module reload fix
- NBIO 6.3.2 support
- IH 7.1 updates
- DC cursor fixes
- VCN/JPEG user fence fixes
- DC support for connectors without DDC
- Prefer ROM BAR for default VGA device
- DC bandwidth fixes
- Add PTL support for profiler
- Introduce dc_plane_cm and migrate surface update color path
- Add FRL registers for HDMI 2.1
- Restructure VM state machine
- Auxless ALPM support
- GEM_OP locking/warning fixes
- switch to system_dfl_wq
amdkfd:
- GPUVM TLB flush fix
- Hotplug fix
- Boundary check fixes
- SVM fixes
- CRIU fixes
- add profiler API
- MES 12.1 updates
msm:
- core:
- fix shrinker documentation
- IFPC enabled for gen8
- PERFCNTR_CONFIG ioctl support
- GPU:
- reworked UBWC handling
- a810 support
- MDSS:
- add support for Milos platform
- reworked UBWC handling
- DisplayPort:
- reworked HPD handling as prep for MST
- DPU:
- Milos platform support
- reworked UBWC handling
- DSI:
- Milos platform support
nova:
- Hopper/Blackwell enablement (GH100/GB100/GB202)
- FSP support
- 32-bit firmware support
- HAL functions
- refactor GSP boot/unload
- GA100 support
- VBIOS hardening/refactoring
- Adopt higher order lifetime types
tyr:
- define register blocks
- add shmem backed GEM objects
- adopt higher order lifetime types
- move clock cleanup into Drop
radeon:
- Hawaii SMU fixes
- CS parser fix
- use struct drm_edid instead of edid
amdxdna:
- export per-client BO memory via fdinfo
- AIE4 device support
- support medium/lower power modes
- expandable device heap support
- revert read-only user-pointer BO mappings
ivpu:
- support frequency limiting
panthor:
- enable GEM shrinker support
- add eviction and reclaim info to fdinfo
v3d:
- enable runtime PM
mgag200:
- support XRGB1555 + C8
ast:
- support XRGB1555 + C8
- use constants for lots of registers
- fix register handling
imagination:
- fence handling refactoring
nouveau:
- fix sched double call
- expose VBIOS on GSP-RM systems
- add GA100 support
virtio:
- add VIRTIO_GPU_F_BLOB_ALIGNMENT flag
- add deferred mapping support
gud:
- add RCade Display Adapter
hibmc:
- fix no connectors usage
mediatek:
- hdmi: convert error handling
- simplify mtk_crtc allocation
exynos:
- move fbdev emulation to drm client buffers
- use drm format helpers for geometry/size
- adopt core DMA tracking
- fix framebuffer offset handling
renesas:
- add RZ/T2H SOC support
versilicon:
- add cursor plane support
tegra:
- use drm client for framebuffer"
* tag 'drm-next-2026-06-17' of https://gitlab.freedesktop.org/drm/kernel: (1731 commits)
dma-buf: move system_cc_shared heap under separate Kconfig
accel/amdxdna: Clear sva pointer after unbind
agp/amd64: Fix broken error propagation in agp_amd64_probe()
accel/amdxdna: Require carveout when PASID and force_iova are disabled
drm/amdkfd: always resume_all after suspend_all
drm/amdgpu/gfx: move fault and EOP IRQ get/put to hw_init/hw_fini
drm/amd/display: Consult MCCS FreeSync cap only if requested & supported
drm/amd/pm: Use strscpy in profile mode parsing
drm/amdkfd: Fix infinite loop parsing CRAT with zero subtype length
drm/amdkfd: fix sysfs topology prop length on buffer truncation
drm/amdgpu: drop retry loop in amdgpu_hmm_range_get_pages
drm/amd/pm: bound OD parameter parsing to stack array size
drm/amd/pm: Stop pp_od_clk_voltage emit at PAGE_SIZE
drm/amdkfd: Unwind debug trap enable on copy_to_user failure
drm/amdgpu: validate the mes firmware version for gfx12.1
drm/amdgpu: validate the mes firmware version for gfx12
drm/amdgpu: compare MES firmware version ucode for gfx11
drm/amdkfd: Add bounds check for AMDKFD_IOC_WAIT_EVENTS
drm/amdgpu: restart the CS if some parts of the VM are still invalidated
drm/amd/display: use unsigned types for local pipe and REG_GET counters
...
666 lines
21 KiB
Rust
666 lines
21 KiB
Rust
// SPDX-License-Identifier: GPL-2.0
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// SPDX-FileCopyrightText: Copyright (c) 2025-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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//! Contains structures and functions dedicated to the parsing, building and patching of firmwares
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//! to be loaded into a given execution unit.
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use core::marker::PhantomData;
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use core::ops::Deref;
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use kernel::{
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device,
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firmware,
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prelude::*,
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str::CString,
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transmute::FromBytes, //
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};
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use crate::{
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falcon::{
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FalconDmaLoadTarget,
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FalconFirmware, //
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},
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gpu,
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num::{
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FromSafeCast,
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IntoSafeCast, //
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},
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};
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pub(crate) mod booter;
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pub(crate) mod fsp;
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pub(crate) mod fwsec;
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pub(crate) mod gsp;
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pub(crate) mod riscv;
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pub(crate) const FIRMWARE_VERSION: &str = "570.144";
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/// Requests the GPU firmware `name` suitable for `chipset`, with version `ver`.
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fn request_firmware(
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dev: &device::Device,
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chipset: gpu::Chipset,
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name: &str,
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ver: &str,
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) -> Result<firmware::Firmware> {
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let chip_name = chipset.name();
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CString::try_from_fmt(fmt!("nvidia/{chip_name}/gsp/{name}-{ver}.bin"))
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.and_then(|path| firmware::Firmware::request(&path, dev))
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}
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/// Structure used to describe some firmwares, notably FWSEC-FRTS.
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#[repr(C)]
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#[derive(Debug, Clone, FromBytes)]
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pub(crate) struct FalconUCodeDescV2 {
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/// Header defined by 'NV_BIT_FALCON_UCODE_DESC_HEADER_VDESC*' in OpenRM.
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hdr: u32,
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/// Stored size of the ucode after the header, compressed or uncompressed
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stored_size: u32,
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/// Uncompressed size of the ucode. If store_size == uncompressed_size, then the ucode
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/// is not compressed.
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pub(crate) uncompressed_size: u32,
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/// Code entry point
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pub(crate) virtual_entry: u32,
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/// Offset after the code segment at which the Application Interface Table headers are located.
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pub(crate) interface_offset: u32,
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/// Base address at which to load the code segment into 'IMEM'.
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pub(crate) imem_phys_base: u32,
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/// Size in bytes of the code to copy into 'IMEM' (includes both secure and non-secure
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/// segments).
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pub(crate) imem_load_size: u32,
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/// Virtual 'IMEM' address (i.e. 'tag') at which the code should start.
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pub(crate) imem_virt_base: u32,
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/// Virtual address of secure IMEM segment.
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pub(crate) imem_sec_base: u32,
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/// Size of secure IMEM segment.
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pub(crate) imem_sec_size: u32,
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/// Offset into stored (uncompressed) image at which DMEM begins.
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pub(crate) dmem_offset: u32,
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/// Base address at which to load the data segment into 'DMEM'.
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pub(crate) dmem_phys_base: u32,
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/// Size in bytes of the data to copy into 'DMEM'.
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pub(crate) dmem_load_size: u32,
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/// "Alternate" Size of data to load into IMEM.
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pub(crate) alt_imem_load_size: u32,
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/// "Alternate" Size of data to load into DMEM.
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pub(crate) alt_dmem_load_size: u32,
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}
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/// Structure used to describe some firmwares, notably FWSEC-FRTS.
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#[repr(C)]
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#[derive(Debug, Clone)]
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pub(crate) struct FalconUCodeDescV3 {
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/// Header defined by `NV_BIT_FALCON_UCODE_DESC_HEADER_VDESC*` in OpenRM.
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hdr: u32,
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/// Stored size of the ucode after the header.
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stored_size: u32,
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/// Offset in `DMEM` at which the signature is expected to be found.
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pub(crate) pkc_data_offset: u32,
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/// Offset after the code segment at which the app headers are located.
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pub(crate) interface_offset: u32,
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/// Base address at which to load the code segment into `IMEM`.
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pub(crate) imem_phys_base: u32,
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/// Size in bytes of the code to copy into `IMEM`.
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pub(crate) imem_load_size: u32,
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/// Virtual `IMEM` address (i.e. `tag`) at which the code should start.
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pub(crate) imem_virt_base: u32,
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/// Base address at which to load the data segment into `DMEM`.
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pub(crate) dmem_phys_base: u32,
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/// Size in bytes of the data to copy into `DMEM`.
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pub(crate) dmem_load_size: u32,
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/// Mask of the falcon engines on which this firmware can run.
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pub(crate) engine_id_mask: u16,
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/// ID of the ucode used to infer a fuse register to validate the signature.
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pub(crate) ucode_id: u8,
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/// Number of signatures in this firmware.
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pub(crate) signature_count: u8,
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/// Versions of the signatures, used to infer a valid signature to use.
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pub(crate) signature_versions: u16,
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_reserved: u16,
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}
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// SAFETY: all bit patterns are valid for this type, and it doesn't use
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// interior mutability.
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unsafe impl FromBytes for FalconUCodeDescV3 {}
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/// Enum wrapping the different versions of Falcon microcode descriptors.
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///
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/// This allows handling both V2 and V3 descriptor formats through a
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/// unified type, providing version-agnostic access to firmware metadata
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/// via the [`FalconUCodeDescriptor`] trait.
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#[derive(Debug, Clone)]
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pub(crate) enum FalconUCodeDesc {
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V2(FalconUCodeDescV2),
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V3(FalconUCodeDescV3),
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}
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impl Deref for FalconUCodeDesc {
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type Target = dyn FalconUCodeDescriptor;
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fn deref(&self) -> &Self::Target {
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match self {
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FalconUCodeDesc::V2(v2) => v2,
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FalconUCodeDesc::V3(v3) => v3,
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}
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}
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}
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/// Trait providing a common interface for accessing Falcon microcode descriptor fields.
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///
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/// This trait abstracts over the different descriptor versions ([`FalconUCodeDescV2`] and
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/// [`FalconUCodeDescV3`]), allowing code to work with firmware metadata without needing to
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/// know the specific descriptor version. Fields not present return zero.
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pub(crate) trait FalconUCodeDescriptor {
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fn hdr(&self) -> u32;
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fn imem_load_size(&self) -> u32;
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fn interface_offset(&self) -> u32;
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fn dmem_load_size(&self) -> u32;
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fn pkc_data_offset(&self) -> u32;
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fn engine_id_mask(&self) -> u16;
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fn ucode_id(&self) -> u8;
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fn signature_count(&self) -> u8;
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fn signature_versions(&self) -> u16;
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/// Returns the size in bytes of the header.
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fn size(&self) -> usize {
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let hdr = self.hdr();
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const HDR_SIZE_SHIFT: u32 = 16;
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const HDR_SIZE_MASK: u32 = 0xffff0000;
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((hdr & HDR_SIZE_MASK) >> HDR_SIZE_SHIFT).into_safe_cast()
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}
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fn imem_sec_load_params(&self) -> FalconDmaLoadTarget;
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fn imem_ns_load_params(&self) -> Option<FalconDmaLoadTarget>;
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fn dmem_load_params(&self) -> FalconDmaLoadTarget;
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}
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impl FalconUCodeDescriptor for FalconUCodeDescV2 {
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fn hdr(&self) -> u32 {
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self.hdr
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}
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fn imem_load_size(&self) -> u32 {
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self.imem_load_size
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}
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fn interface_offset(&self) -> u32 {
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self.interface_offset
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}
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fn dmem_load_size(&self) -> u32 {
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self.dmem_load_size
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}
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fn pkc_data_offset(&self) -> u32 {
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0
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}
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fn engine_id_mask(&self) -> u16 {
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0
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}
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fn ucode_id(&self) -> u8 {
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0
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}
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fn signature_count(&self) -> u8 {
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0
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}
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fn signature_versions(&self) -> u16 {
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0
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}
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fn imem_sec_load_params(&self) -> FalconDmaLoadTarget {
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// `imem_sec_base` is the *virtual* start address of the secure IMEM segment, so subtract
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// `imem_virt_base` to get its physical offset.
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let imem_sec_start = self.imem_sec_base.saturating_sub(self.imem_virt_base);
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FalconDmaLoadTarget {
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src_start: imem_sec_start,
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dst_start: self.imem_phys_base.saturating_add(imem_sec_start),
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len: self.imem_sec_size,
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}
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}
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fn imem_ns_load_params(&self) -> Option<FalconDmaLoadTarget> {
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Some(FalconDmaLoadTarget {
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// Non-secure code always starts at offset 0.
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src_start: 0,
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dst_start: self.imem_phys_base,
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// `imem_load_size` includes the size of the secure segment, so subtract it to
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// get the correct amount of data to copy.
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len: self.imem_load_size.saturating_sub(self.imem_sec_size),
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})
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}
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fn dmem_load_params(&self) -> FalconDmaLoadTarget {
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FalconDmaLoadTarget {
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src_start: self.dmem_offset,
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dst_start: self.dmem_phys_base,
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len: self.dmem_load_size,
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}
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}
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}
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impl FalconUCodeDescriptor for FalconUCodeDescV3 {
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fn hdr(&self) -> u32 {
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self.hdr
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}
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fn imem_load_size(&self) -> u32 {
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self.imem_load_size
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}
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fn interface_offset(&self) -> u32 {
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self.interface_offset
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}
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fn dmem_load_size(&self) -> u32 {
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self.dmem_load_size
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}
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fn pkc_data_offset(&self) -> u32 {
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self.pkc_data_offset
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}
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fn engine_id_mask(&self) -> u16 {
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self.engine_id_mask
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}
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fn ucode_id(&self) -> u8 {
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self.ucode_id
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}
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fn signature_count(&self) -> u8 {
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self.signature_count
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}
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fn signature_versions(&self) -> u16 {
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self.signature_versions
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}
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fn imem_sec_load_params(&self) -> FalconDmaLoadTarget {
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FalconDmaLoadTarget {
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// IMEM segment always starts at offset 0.
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src_start: 0,
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dst_start: self.imem_phys_base,
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len: self.imem_load_size,
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}
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}
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fn imem_ns_load_params(&self) -> Option<FalconDmaLoadTarget> {
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// Not used on V3 platforms
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None
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}
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fn dmem_load_params(&self) -> FalconDmaLoadTarget {
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FalconDmaLoadTarget {
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// DMEM segment starts right after the IMEM one.
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src_start: self.imem_load_size,
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dst_start: self.dmem_phys_base,
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len: self.dmem_load_size,
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}
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}
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}
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/// Trait implemented by types defining the signed state of a firmware.
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trait SignedState {}
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/// Type indicating that the firmware must be signed before it can be used.
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struct Unsigned;
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impl SignedState for Unsigned {}
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/// Type indicating that the firmware is signed and ready to be loaded.
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struct Signed;
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impl SignedState for Signed {}
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/// Microcode to be loaded into a specific falcon.
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///
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/// This is module-local and meant for sub-modules to use internally.
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///
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/// After construction, a firmware is [`Unsigned`], and must generally be patched with a signature
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/// before it can be loaded (with an exception for development hardware). The
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/// [`Self::patch_signature`] and [`Self::no_patch_signature`] methods are used to transition the
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/// firmware to its [`Signed`] state.
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// TODO: Consider replacing this with a coherent memory object once `CoherentAllocation` supports
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// temporary CPU-exclusive access to the object without unsafe methods.
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struct FirmwareObject<F: FalconFirmware, S: SignedState>(KVVec<u8>, PhantomData<(F, S)>);
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/// Trait for signatures to be patched directly into a given firmware.
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///
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/// This is module-local and meant for sub-modules to use internally.
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trait FirmwareSignature<F: FalconFirmware>: AsRef<[u8]> {}
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impl<F: FalconFirmware> FirmwareObject<F, Unsigned> {
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/// Patches the firmware at offset `signature_start` with `signature`.
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fn patch_signature<S: FirmwareSignature<F>>(
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mut self,
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signature: &S,
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signature_start: usize,
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) -> Result<FirmwareObject<F, Signed>> {
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let signature_bytes = signature.as_ref();
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let signature_end = signature_start
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.checked_add(signature_bytes.len())
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.ok_or(EOVERFLOW)?;
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let dst = self
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.0
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.get_mut(signature_start..signature_end)
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.ok_or(EINVAL)?;
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// PANIC: `dst` and `signature_bytes` have the same length.
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dst.copy_from_slice(signature_bytes);
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Ok(FirmwareObject(self.0, PhantomData))
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}
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/// Mark the firmware as signed without patching it.
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///
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/// This method is used to explicitly confirm that we do not need to sign the firmware, while
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/// allowing us to continue as if it was. This is typically only needed for development
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/// hardware.
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fn no_patch_signature(self) -> FirmwareObject<F, Signed> {
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FirmwareObject(self.0, PhantomData)
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}
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}
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/// Header common to most firmware files.
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#[repr(C)]
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#[derive(Debug, Clone)]
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struct BinHdr {
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/// Magic number, must be `0x10de`.
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bin_magic: u32,
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/// Version of the header.
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bin_ver: u32,
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/// Size in bytes of the binary (to be ignored).
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bin_size: u32,
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/// Offset of the start of the application-specific header.
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header_offset: u32,
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/// Offset of the start of the data payload.
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data_offset: u32,
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/// Size in bytes of the data payload.
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data_size: u32,
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}
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// SAFETY: all bit patterns are valid for this type, and it doesn't use interior mutability.
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unsafe impl FromBytes for BinHdr {}
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// A firmware blob starting with a `BinHdr`.
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struct BinFirmware<'a> {
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hdr: BinHdr,
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fw: &'a [u8],
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}
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impl<'a> BinFirmware<'a> {
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/// Interpret `fw` as a firmware image starting with a [`BinHdr`], and returns the
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/// corresponding [`BinFirmware`] that can be used to extract its payload.
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fn new(fw: &'a firmware::Firmware) -> Result<Self> {
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const BIN_MAGIC: u32 = 0x10de;
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let fw = fw.data();
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fw.get(0..size_of::<BinHdr>())
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// Extract header.
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.and_then(BinHdr::from_bytes_copy)
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// Validate header.
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.filter(|hdr| hdr.bin_magic == BIN_MAGIC)
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.map(|hdr| Self { hdr, fw })
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.ok_or(EINVAL)
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}
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/// Returns the data payload of the firmware, or `None` if the data range is out of bounds of
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/// the firmware image.
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fn data(&self) -> Option<&[u8]> {
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let fw_start = usize::from_safe_cast(self.hdr.data_offset);
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let fw_size = usize::from_safe_cast(self.hdr.data_size);
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let fw_end = fw_start.checked_add(fw_size)?;
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self.fw.get(fw_start..fw_end)
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}
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}
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pub(crate) struct ModInfoBuilder<const N: usize>(firmware::ModInfoBuilder<N>);
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impl<const N: usize> ModInfoBuilder<N> {
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const fn make_entry_file(self, chipset: &str, fw: &str) -> Self {
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ModInfoBuilder(
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self.0
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.new_entry()
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.push("nvidia/")
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.push(chipset)
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.push("/gsp/")
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.push(fw)
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.push("-")
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.push(FIRMWARE_VERSION)
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.push(".bin"),
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)
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}
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const fn make_entry_chipset(self, chipset: gpu::Chipset) -> Self {
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let name = chipset.name();
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let this = self
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.make_entry_file(name, "booter_load")
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.make_entry_file(name, "booter_unload")
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.make_entry_file(name, "bootloader")
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.make_entry_file(name, "gsp");
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let this = if chipset.needs_fwsec_bootloader() {
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this.make_entry_file(name, "gen_bootloader")
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} else {
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this
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};
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if chipset.uses_fsp() {
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this.make_entry_file(name, "fmc")
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} else {
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this
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}
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}
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pub(crate) const fn create(
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module_name: &'static core::ffi::CStr,
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) -> firmware::ModInfoBuilder<N> {
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let mut this = Self(firmware::ModInfoBuilder::new(module_name));
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let mut i = 0;
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while i < gpu::Chipset::ALL.len() {
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this = this.make_entry_chipset(gpu::Chipset::ALL[i]);
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i += 1;
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}
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this.0
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}
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}
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/// Ad-hoc and temporary module to extract sections from ELF images.
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///
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/// Some firmware images are currently packaged as ELF files, where sections names are used as keys
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/// to specific and related bits of data. Future firmware versions are scheduled to move away from
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/// that scheme before nova-core becomes stable, which means this module will eventually be
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/// removed.
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mod elf {
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use core::mem::size_of;
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use kernel::{
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bindings,
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str::CStr,
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transmute::FromBytes, //
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};
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/// Trait to abstract over ELF header differences.
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trait ElfHeader: FromBytes {
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fn shnum(&self) -> u16;
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fn shoff(&self) -> u64;
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fn shstrndx(&self) -> u16;
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}
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/// Trait to abstract over ELF section-header differences.
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trait ElfSectionHeader: FromBytes {
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fn name(&self) -> u32;
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fn offset(&self) -> u64;
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fn size(&self) -> u64;
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}
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/// Trait describing a matching ELF header and section-header format.
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trait ElfFormat {
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type Header: ElfHeader;
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type SectionHeader: ElfSectionHeader;
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}
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/// Newtype to provide a [`FromBytes`] implementation.
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#[repr(transparent)]
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struct Elf64Hdr(bindings::elf64_hdr);
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// SAFETY: all bit patterns are valid for this type, and it doesn't use interior mutability.
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unsafe impl FromBytes for Elf64Hdr {}
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impl ElfHeader for Elf64Hdr {
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fn shnum(&self) -> u16 {
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self.0.e_shnum
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}
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fn shoff(&self) -> u64 {
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self.0.e_shoff
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}
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fn shstrndx(&self) -> u16 {
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self.0.e_shstrndx
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}
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}
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#[repr(transparent)]
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struct Elf64SHdr(bindings::elf64_shdr);
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// SAFETY: all bit patterns are valid for this type, and it doesn't use interior mutability.
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unsafe impl FromBytes for Elf64SHdr {}
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impl ElfSectionHeader for Elf64SHdr {
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fn name(&self) -> u32 {
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self.0.sh_name
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}
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fn offset(&self) -> u64 {
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self.0.sh_offset
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}
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fn size(&self) -> u64 {
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self.0.sh_size
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}
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}
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struct Elf64Format;
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impl ElfFormat for Elf64Format {
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type Header = Elf64Hdr;
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type SectionHeader = Elf64SHdr;
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}
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/// Newtype to provide [`FromBytes`] and [`ElfHeader`] implementations for ELF32.
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#[repr(transparent)]
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struct Elf32Hdr(bindings::elf32_hdr);
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// SAFETY: all bit patterns are valid for this type, and it doesn't use interior mutability.
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unsafe impl FromBytes for Elf32Hdr {}
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impl ElfHeader for Elf32Hdr {
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fn shnum(&self) -> u16 {
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self.0.e_shnum
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}
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fn shoff(&self) -> u64 {
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u64::from(self.0.e_shoff)
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}
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fn shstrndx(&self) -> u16 {
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self.0.e_shstrndx
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}
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}
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/// Newtype to provide [`FromBytes`] and [`ElfSectionHeader`] implementations for ELF32.
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#[repr(transparent)]
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struct Elf32SHdr(bindings::elf32_shdr);
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// SAFETY: all bit patterns are valid for this type, and it doesn't use interior mutability.
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unsafe impl FromBytes for Elf32SHdr {}
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impl ElfSectionHeader for Elf32SHdr {
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fn name(&self) -> u32 {
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self.0.sh_name
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}
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fn offset(&self) -> u64 {
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u64::from(self.0.sh_offset)
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}
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fn size(&self) -> u64 {
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u64::from(self.0.sh_size)
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}
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}
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struct Elf32Format;
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impl ElfFormat for Elf32Format {
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type Header = Elf32Hdr;
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type SectionHeader = Elf32SHdr;
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}
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/// Returns a NULL-terminated string from the ELF image at `offset`.
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fn elf_str(elf: &[u8], offset: u64) -> Option<&str> {
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let idx = usize::try_from(offset).ok()?;
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let bytes = elf.get(idx..)?;
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CStr::from_bytes_until_nul(bytes).ok()?.to_str().ok()
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}
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fn elf_section_generic<'a, F>(elf: &'a [u8], name: &str) -> Option<&'a [u8]>
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where
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F: ElfFormat,
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{
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let hdr = F::Header::from_bytes(elf.get(0..size_of::<F::Header>())?)?;
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let shdr_num = usize::from(hdr.shnum());
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let shdr_start = usize::try_from(hdr.shoff()).ok()?;
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let shdr_end = shdr_num
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.checked_mul(size_of::<F::SectionHeader>())
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.and_then(|v| v.checked_add(shdr_start))?;
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// Get all the section headers as an iterator over byte chunks.
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let shdr_bytes = elf.get(shdr_start..shdr_end)?;
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let mut shdr_iter = shdr_bytes.chunks_exact(size_of::<F::SectionHeader>());
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// Get the strings table.
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let strhdr = shdr_iter
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.clone()
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.nth(usize::from(hdr.shstrndx()))
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.and_then(F::SectionHeader::from_bytes)?;
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// Find the section which name matches `name` and return it.
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shdr_iter.find_map(|sh_bytes| {
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let sh = F::SectionHeader::from_bytes(sh_bytes)?;
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let name_offset = strhdr.offset().checked_add(u64::from(sh.name()))?;
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let section_name = elf_str(elf, name_offset)?;
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if section_name != name {
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return None;
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}
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let start = usize::try_from(sh.offset()).ok()?;
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let end = usize::try_from(sh.size())
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.ok()
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.and_then(|sz| start.checked_add(sz))?;
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elf.get(start..end)
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})
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}
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/// Extract the section with name `name` from the ELF64 image `elf`.
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fn elf64_section<'a>(elf: &'a [u8], name: &str) -> Option<&'a [u8]> {
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elf_section_generic::<Elf64Format>(elf, name)
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}
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/// Extract the section with name `name` from the ELF32 image `elf`.
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fn elf32_section<'a>(elf: &'a [u8], name: &str) -> Option<&'a [u8]> {
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elf_section_generic::<Elf32Format>(elf, name)
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}
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/// Automatically detects ELF32 vs ELF64 based on the ELF header.
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pub(super) fn elf_section<'a>(elf: &'a [u8], name: &str) -> Option<&'a [u8]> {
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// ELF identification: a 4-byte magic followed by a class byte (32- vs 64-bit).
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const ELFMAG: &[u8] = b"\x7fELF";
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const SELFMAG: usize = ELFMAG.len();
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const EI_CLASS: usize = 4;
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const ELFCLASS32: u8 = 1;
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const ELFCLASS64: u8 = 2;
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if elf.get(0..SELFMAG) != Some(ELFMAG) {
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return None;
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}
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match *elf.get(EI_CLASS)? {
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ELFCLASS32 => elf32_section(elf, name),
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ELFCLASS64 => elf64_section(elf, name),
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_ => None,
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}
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}
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}
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