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0810d5ad88
Using the DRM GPU scheduler infrastructure, with a scheduler for each core. Userspace can decide for a series of tasks to be executed sequentially in the same core, so SRAM locality can be taken advantage of. The job submission code was initially based on Panfrost. v2: - Remove hardcoded number of cores - Misc. style fixes (Jeffrey Hugo) - Repack IOCTL struct (Jeffrey Hugo) v3: - Adapt to a split of the register block in the DT bindings (Nicolas Frattaroli) - Make use of GPL-2.0-only for the copyright notice (Jeff Hugo) - Use drm_* logging functions (Thomas Zimmermann) - Rename reg i/o macros (Thomas Zimmermann) - Add padding to ioctls and check for zero (Jeff Hugo) - Improve error handling (Nicolas Frattaroli) v6: - Use mutexes guard (Markus Elfring) - Use u64_to_user_ptr (Jeff Hugo) - Drop rocket_fence (Rob Herring) v7: - Assign its own IOMMU domain to each client, for isolation (Daniel Stone and Robin Murphy) v8: - Use reset lines to reset the cores (Robin Murphy) - Use the macros to compute the values for the bitfields (Robin Murphy) - More descriptive name for the IRQ (Robin Murphy) - Simplify job interrupt handing (Robin Murphy) - Correctly acquire a reference to the IOMMU (Robin Murphy) - Specify the size of the embedded structs in the IOCTLs for future extensibility (Rob Herring) - Expose only 32 bits for the address of the regcmd BO (Robin Murphy) Tested-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Jeff Hugo <jeff.hugo@oss.qualcomm.com> Signed-off-by: Tomeu Vizoso <tomeu@tomeuvizoso.net> Signed-off-by: Jeff Hugo <jeff.hugo@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250721-6-10-rocket-v9-4-77ebd484941e@tomeuvizoso.net
111 lines
2.9 KiB
C
111 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright 2024-2025 Tomeu Vizoso <tomeu@tomeuvizoso.net> */
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/dev_printk.h>
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#include <linux/dma-mapping.h>
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#include <linux/err.h>
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#include <linux/iommu.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/reset.h>
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#include "rocket_core.h"
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#include "rocket_job.h"
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int rocket_core_init(struct rocket_core *core)
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{
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struct device *dev = core->dev;
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struct platform_device *pdev = to_platform_device(dev);
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u32 version;
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int err = 0;
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core->resets[0].id = "srst_a";
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core->resets[1].id = "srst_h";
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err = devm_reset_control_bulk_get_exclusive(&pdev->dev, ARRAY_SIZE(core->resets),
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core->resets);
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if (err)
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return dev_err_probe(dev, err, "failed to get resets for core %d\n", core->index);
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err = devm_clk_bulk_get(dev, ARRAY_SIZE(core->clks), core->clks);
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if (err)
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return dev_err_probe(dev, err, "failed to get clocks for core %d\n", core->index);
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core->pc_iomem = devm_platform_ioremap_resource_byname(pdev, "pc");
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if (IS_ERR(core->pc_iomem)) {
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dev_err(dev, "couldn't find PC registers %ld\n", PTR_ERR(core->pc_iomem));
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return PTR_ERR(core->pc_iomem);
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}
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core->cna_iomem = devm_platform_ioremap_resource_byname(pdev, "cna");
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if (IS_ERR(core->cna_iomem)) {
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dev_err(dev, "couldn't find CNA registers %ld\n", PTR_ERR(core->cna_iomem));
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return PTR_ERR(core->cna_iomem);
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}
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core->core_iomem = devm_platform_ioremap_resource_byname(pdev, "core");
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if (IS_ERR(core->core_iomem)) {
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dev_err(dev, "couldn't find CORE registers %ld\n", PTR_ERR(core->core_iomem));
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return PTR_ERR(core->core_iomem);
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}
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dma_set_max_seg_size(dev, UINT_MAX);
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err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
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if (err)
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return err;
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core->iommu_group = iommu_group_get(dev);
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err = rocket_job_init(core);
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if (err)
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return err;
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pm_runtime_use_autosuspend(dev);
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/*
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* As this NPU will be most often used as part of a media pipeline that
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* ends presenting in a display, choose 50 ms (~3 frames at 60Hz) as an
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* autosuspend delay as that will keep the device powered up while the
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* pipeline is running.
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*/
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pm_runtime_set_autosuspend_delay(dev, 50);
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pm_runtime_enable(dev);
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err = pm_runtime_get_sync(dev);
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if (err) {
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rocket_job_fini(core);
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return err;
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}
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version = rocket_pc_readl(core, VERSION);
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version += rocket_pc_readl(core, VERSION_NUM) & 0xffff;
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pm_runtime_mark_last_busy(dev);
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pm_runtime_put_autosuspend(dev);
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dev_info(dev, "Rockchip NPU core %d version: %d\n", core->index, version);
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return 0;
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}
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void rocket_core_fini(struct rocket_core *core)
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{
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pm_runtime_dont_use_autosuspend(core->dev);
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pm_runtime_disable(core->dev);
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iommu_group_put(core->iommu_group);
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core->iommu_group = NULL;
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rocket_job_fini(core);
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}
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void rocket_core_reset(struct rocket_core *core)
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{
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reset_control_bulk_assert(ARRAY_SIZE(core->resets), core->resets);
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udelay(10);
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reset_control_bulk_deassert(ARRAY_SIZE(core->resets), core->resets);
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}
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