Heiner Kallweit e508cea45b
spi: fsl-espi: make better use of the RX FIFO ...
So far an interrupt is triggered whenever there's at least one byte
in the RX FIFO. This results in a unnecessarily high number of
interrupts.
Change this to generate an interrupt if
- RX FIFO is half full (except if all bytes to read fit into the
RX FIFO anyway)
- end of transfer has been reached
This way the number of interrupts can be significantly reduced.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com >
Signed-off-by: Mark Brown <broonie@kernel.org >
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e508cea45b