Changbin Du e1236bc06c drm/i915/gvt: Align render mmio list to cacheline ...

Make the global mmio list be cacheline aligned to improve performance.

Signed-off-by: Changbin Du <changbin.du@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>

2017-04-12 13:57:42 +08:00

..

drm

drm/i915/gvt: Align render mmio list to cacheline

2017-04-12 13:57:42 +08:00

host1x

gpu: host1x: Set OF node for new host1x devices

2017-01-30 11:47:44 +01:00

ipu-v3

gpu: ipu-v3: only set non-zero AXI ID for IC when PRG is absent

2017-03-16 10:14:49 +01:00

vga

Merge tag 'doc-4.11-images' of git://git.lwn.net/linux into drm-misc-next

2017-03-14 15:07:33 +01:00

Makefile

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