Jani Nikula e01163e82b drm/i915/dg2: configure TRANS_DP2_VFREQ{HIGH,LOW} for 128b/132b ...

There's a new register pair for 128b/132b mode where you need to set the
pixel clock in Hz.

v2: Fix UHBR rate check, use intel_dp_is_uhbr() helper

Bspec: 54128
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/a2902cc188973f022f282f2a77e693afdecefb5a.1631191763.git.jani.nikula@intel.com

2021-09-20 18:47:00 +03:00

..

drm

drm/i915/dg2: configure TRANS_DP2_VFREQ{HIGH,LOW} for 128b/132b

2021-09-20 18:47:00 +03:00

host1x

gpu: host1x: debug: Dump DMASTART and DMAEND register

2021-08-13 18:23:32 +02:00

ipu-v3

Merge tag 'irq-core-2021-08-30' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

2021-08-30 14:38:37 -07:00

trace

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vga

vgaarb: don't pass a cookie to vga_client_register

2021-07-21 10:29:10 +02:00

Makefile

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