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Martin Blumenstingl 9fac2a193e dt-bindings: mtd: intel: lgm-nand: Fix maximum chip select value
The Intel LGM NAND IP only supports two chip selects: There's only two
CS and ADDR_SEL register sets. Fix the maximum allowed chip select value
according to the dt-bindings.

Fixes: 2f9cea8eae ("dt-bindings: mtd: Add Nand Flash Controller support for Intel LGM SoC")
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20220702231227.1579176-3-martin.blumenstingl@googlemail.com
2022-09-20 10:06:47 +02:00
..
2022-08-11 23:25:05 +02:00
2022-07-27 21:18:00 +09:00
2022-07-11 15:51:01 +01:00