Files
linux/drivers/net/phy
Daniel Gorsulowski 2e1ec861a6 net: dp83869: Fix RGMII internal delay configuration
The RGMII control register at 0x32 indicates the states for the bits
RGMII_TX_CLK_DELAY and RGMII_RX_CLK_DELAY as follows:

  RGMII Transmit/Receive Clock Delay
    0x0 = RGMII transmit clock is shifted with respect to transmit/receive data.
    0x1 = RGMII transmit clock is aligned with respect to transmit/receive data.

This commit fixes the inversed behavior of these bits

Fixes: 736b25afe2 ("net: dp83869: Add RGMII internal delay configuration")
Signed-off-by: Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
Acked-by: Dan Murphy <dmurphy@ti.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-08-26 07:13:28 -07:00
..
2020-07-07 12:47:10 -07:00
2019-08-02 17:56:28 -07:00
2020-06-19 20:17:15 -07:00