Deepak S db5ff4ac97 drm/i915: Forcewake Register Range changes for CHV ...

According to updated BSpec, Render/Common/media Wells register range changed.
Updating the same to match the spec and avoid extra forcewake for none
forcewake range.

v2: Update media forcewake range (Ville)

Signed-off-by: Deepak S <deepak.s@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

2014-12-15 09:54:23 +01:00

..

drm

drm/i915: Forcewake Register Range changes for CHV

2014-12-15 09:54:23 +01:00

host1x

gpu: host1x: mipi: Set MIPI_CAL_BIAS_PAD_CFG1 register

2014-11-13 16:11:57 +01:00

ipu-v3

Merge tag 'ipu-fixes-3.18' of git://git.pengutronix.de/git/pza/linux into drm-next

2014-10-07 14:31:14 +10:00

vga

Merge branch 'sched-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

2014-10-13 16:23:15 +02:00

Makefile

gpu: ipu-v3: Move i.MX IPUv3 core driver out of staging

2014-06-04 11:06:52 +02:00