Bjorn Helgaas 78e531d3e5 Merge branch 'pci/controller/tlp_macros' ...

- Add common TLP Type macros (MRd/Wr, IORd/Wr, CfgRd/Wr 0, CfgRd/Wr 1, Msg)
  and use them in aspeed, cadence, dwc, mediatek, tegra drivers (Hans
  Zhang)

* pci/controller/tlp_macros:
  PCI: cadence: Use common TLP type macros
  PCI: dwc: Replace ATU type macros with common TLP type macros
  PCI: Add common TLP type macros and convert aspeed/mediatek

2026-06-23 17:32:23 -05:00

..

Kconfig

PCI: sky1: Add PCIe host support for CIX Sky1

2025-12-02 14:17:55 -06:00

Makefile

PCI: sky1: Add PCIe host support for CIX Sky1

2025-12-02 14:17:55 -06:00

pci-j721e.c

PCI: cadence: Add post-link delay for LGA and j721e glue driver

2026-06-09 20:52:25 +05:30

pci-sky1.c

PCI: sky1: Use boolean true for is_rc field

2026-03-26 23:39:12 +05:30

pcie-cadence-ep.c

PCI: cadence: Search for MSI Capability with correct ID

2025-10-13 16:42:29 -05:00

pcie-cadence-host-common.c

PCI: cadence: Add post-link delay for LGA and j721e glue driver

2026-06-09 20:52:25 +05:30

pcie-cadence-host-common.h

PCI: cadence: Move PCIe RP common functions to a separate file

2025-11-14 22:58:30 +05:30

pcie-cadence-host-hpa.c

PCI: cadence-hpa: Add post-link delay

2026-06-23 14:33:48 -05:00

pcie-cadence-host.c

Merge branch 'pci/controller/rescan_lock'

2026-06-23 17:32:23 -05:00

pcie-cadence-hpa-regs.h

PCI: cadence: Use common TLP type macros

2026-06-09 19:25:07 +05:30

pcie-cadence-hpa.c

PCI: cadence: Add support for High Perf Architecture (HPA) controller

2025-12-02 14:17:03 -06:00

pcie-cadence-lga-regs.h

PCI: cadence: Split PCIe controller header file

2025-11-14 22:58:07 +05:30

pcie-cadence-plat.c

PCI: cadence: Add support for High Perf Architecture (HPA) controller

2025-12-02 14:17:03 -06:00

pcie-cadence.c

PCI: Add preceding capability position support in PCI_FIND_NEXT_*_CAP macros

2025-12-18 12:46:16 +05:30

pcie-cadence.h

PCI: cadence: Add post-link delay for LGA and j721e glue driver

2026-06-09 20:52:25 +05:30

pcie-sg2042.c

PCI: sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root Ports

2026-04-09 13:28:17 -05:00