Maxime Ripard d7d96c00e5 drm/vc4: hvs: Boost the core clock during modeset ...

In order to prevent timeouts and stalls in the pipeline, the core clock
needs to be maxed at 500MHz during a modeset on the BCM2711.

Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Tested-by: Chanwoo Choi <cw00.choi@samsung.com>
Tested-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
Tested-by: Stefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Link: https://patchwork.freedesktop.org/patch/msgid/37ed9e0124c5cce005ddc8dafe821d8b0da036ff.1599120059.git-series.maxime@cerno.tech

2020-09-07 18:01:52 +02:00

..

drm

drm/vc4: hvs: Boost the core clock during modeset

2020-09-07 18:01:52 +02:00

host1x

gpu: host1x: debug: Dump push buffer state

2020-07-17 16:06:14 +02:00

ipu-v3

gpu: ipu-v3: image-convert: Wait for all EOFs before completing a tile

2020-07-20 15:16:05 +02:00

trace

gpu/trace: add a gpu total memory usage tracepoint

2020-03-03 17:52:41 -05:00

vga

vgaarb: mark vga_tryget static

2020-08-01 11:28:17 +02:00

Makefile

gpu/trace: add a gpu total memory usage tracepoint

2020-03-03 17:52:41 -05:00