Alex Deucher f6c3947893 drm/amdgpu: add the VCE 4.0 register headers ...

These are the Video Compression Engine registers for vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2017-03-29 23:54:28 -04:00

..

bif

drm/amd/amdgpu: Introduction of SI registers (v2)

2016-11-11 10:21:07 -05:00

dce

drm/amd/amdgpu: Add DPHY_SCRAM_CNTL register defines

2017-01-27 11:12:44 -05:00

gca

drm/amd/amdgpu: add SI defines/registers

2016-11-11 10:21:08 -05:00

gmc

drm/amdgpu: implement PRT for GFX6 v2

2017-03-29 23:52:57 -04:00

oss

drm/amd/amdgpu: add SI defines/registers

2016-11-11 10:21:08 -05:00

smu

drm/amd/powerplay: add a new register define for APU in VI.

2017-03-29 23:54:06 -04:00

uvd

drm/amd/amdgpu: Introduction of SI registers (v2)

2016-11-11 10:21:07 -05:00

vce

drm/amd/amdgpu: Introduction of SI registers (v2)

2016-11-11 10:21:07 -05:00

vega10

drm/amdgpu: add the VCE 4.0 register headers

2017-03-29 23:54:28 -04:00