Chris Metcalf 32020effaf arch/tile: Fix a couple of issues with the COMPAT code for TILE-Gx. ...

First, the siginfo preamble wasn't quite right; we need to indicate
that we are padding up to 4 ints of preamble for 64-bit code, and
then for compat mode we need to pad differently, using only 3 ints.

Second, the C ABI requires a save area of two registers, not two
pointers, since in compat mode we have 64-bit registers all of which
we need to save, even though we only have 32-bit VAs.

Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>

2010-08-13 08:32:21 -04:00

..

abi.h

arch/tile: Fix a couple of issues with the COMPAT code for TILE-Gx.

2010-08-13 08:32:21 -04:00

chip_tile64.h

arch/tile: Enable more sophisticated IRQ model for 32-bit chips.

2010-07-06 13:34:01 -04:00

chip_tilepro.h

arch/tile: Enable more sophisticated IRQ model for 32-bit chips.

2010-07-06 13:34:01 -04:00

chip.h

arch/tile: core support for Tilera 32-bit chips.

2010-06-04 17:11:18 -04:00

icache.h

arch/tile: Split the icache flush code off to a generic <arch> header.

2010-07-06 13:41:46 -04:00

interrupts_32.h

arch/tile: Miscellaneous cleanup changes.

2010-07-06 13:41:51 -04:00

interrupts.h

arch/tile: core support for Tilera 32-bit chips.

2010-06-04 17:11:18 -04:00

sim_def.h

arch/tile: core support for Tilera 32-bit chips.

2010-06-04 17:11:18 -04:00

spr_def_32.h

arch/tile: core support for Tilera 32-bit chips.

2010-06-04 17:11:18 -04:00

spr_def.h

arch/tile: core support for Tilera 32-bit chips.

2010-06-04 17:11:18 -04:00