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Document xSPI controller found on the Renesas RZ/T2H and RZ/N2H SoCs. The xSPI IP on these SoCs is identical to that found on the RZ/G3E SoC. The RZ/G3E HW manual (Rev.1.15) references bridge channel 1 and its bits, however the hardware actually supports only a single bridge channel (channel 0), matching the RZ/T2H design. The references to channel 1 and its configuration bits will be corrected in a future revision of the HW manual. Update clock/reset constraints to handle the SoC differences. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260515115202.1515577-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>