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Abel Vesa 6487b12a87 dt-bindings: cache: qcom,llcc: Document Eliza LLCC block

Document the Last Level Cache Controller on Eliza SoC. Eliza LLCC has 2
base register regions and an additional AND, OR broadcast region, total 4
register regions.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260513-eliza-llcc-v2-1-27381ae833d5@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

2026-05-21 16:15:49 -05:00

andestech,ax45mp-cache.yaml

dt-bindings: cache: ax45mp: add 2048 as a supported cache-sets value

2025-08-28 17:34:45 +01:00

freescale-l2cache.txt

dt-bindings: move cache controller bindings to a cache directory

2023-04-04 12:12:13 -05:00

l2c2x0.yaml

dt-bindings: Fix array property constraints

2024-10-01 21:17:00 -05:00

marvell,kirkwood-cache.yaml

dt-bindings: cache: Convert marvell,{feroceon,kirkwood}-cache to DT schema