Ville Syrjälä d2d65408cc drm/i915: Enable PCH FIFO underruns later on HSW+ ...

As we did for ILK/SNB/IVB, move the PCH FIFO underrun enable to happen
after the encoder enable on HSW+. And again, for symmetry, move the
the disable to happen before encoder disable.

I've left out the vblank wait before the enable here because I don't
know if it's needed or not. Actually I don't know if this entire
change is needed as I don't have a HSW/BDW with VGA output.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1446146763-31821-5-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

2015-11-10 16:23:06 +02:00

..

drm

drm/i915: Enable PCH FIFO underruns later on HSW+

2015-11-10 16:23:06 +02:00

host1x

gpu: host1x: mipi: Power down regulators when unused

2015-08-13 13:47:21 +02:00

ipu-v3

gpu/drm: Kill off set_irq_flags usage

2015-09-16 16:53:38 +02:00

vga

vga_switcheroo: Set active attribute to false for audio clients

2015-09-24 20:14:25 +02:00

Makefile

gpu: host1x: Provide a proper struct bus_type

2015-01-27 10:09:14 +01:00