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079115370d
The PCIe spec defines two types of streams - selective and link. Each stream has an ID from the same bucket so a stream ID does not tell the type. The spec defines an "enable" bit for every stream and required stream IDs to be unique among all enabled stream but there is no such requirement for disabled streams. However, when IDE_KM is programming keys, an IDE-capable device needs to know the type of stream being programmed to write it directly to the hardware as keys are relatively large, possibly many of them and devices often struggle with keeping around rather big data not being used. Walk through all streams on a device and initialise the IDs to some unique number, both link and selective. The weakest part of this proposal is the host bridge ide_stream_ids_ida. Technically, a Stream ID only needs to be unique within a given partner pair. However, with "anonymous" / unassigned streams there is no convenient place to track the available ids. Proceed with an ida in the host bridge for now, but consider moving this tracking to be an ide_stream_ids_ida per device. Co-developed-by: Alexey Kardashevskiy <aik@amd.com> Signed-off-by: Alexey Kardashevskiy <aik@amd.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Link: https://patch.msgid.link/20251113021446.436830-6-dan.j.williams@intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
120 lines
4.2 KiB
C
120 lines
4.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Common helpers for drivers (e.g. low-level PCI/TSM drivers) implementing the
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* IDE key management protocol (IDE_KM) as defined by:
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* PCIe r7.0 section 6.33 Integrity & Data Encryption (IDE)
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*
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* Copyright(c) 2024-2025 Intel Corporation. All rights reserved.
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*/
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#ifndef __PCI_IDE_H__
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#define __PCI_IDE_H__
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enum pci_ide_partner_select {
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PCI_IDE_EP,
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PCI_IDE_RP,
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PCI_IDE_PARTNER_MAX,
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/*
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* In addition to the resources in each partner port the
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* platform / host-bridge additionally has a Stream ID pool that
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* it shares across root ports. Let pci_ide_stream_alloc() use
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* the alloc_stream_index() helper as endpoints and root ports.
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*/
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PCI_IDE_HB = PCI_IDE_PARTNER_MAX,
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};
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/**
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* struct pci_ide_partner - Per port pair Selective IDE Stream settings
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* @rid_start: Partner Port Requester ID range start
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* @rid_end: Partner Port Requester ID range end
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* @stream_index: Selective IDE Stream Register Block selection
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* @mem_assoc: PCI bus memory address association for targeting peer partner
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* @pref_assoc: PCI bus prefetchable memory address association for
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* targeting peer partner
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* @default_stream: Endpoint uses this stream for all upstream TLPs regardless of
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* address and RID association registers
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* @setup: flag to track whether to run pci_ide_stream_teardown() for this
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* partner slot
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* @enable: flag whether to run pci_ide_stream_disable() for this partner slot
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*
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* By default, pci_ide_stream_alloc() initializes @mem_assoc and @pref_assoc
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* with the immediate ancestor downstream port memory ranges (i.e. Type 1
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* Configuration Space Header values). Caller may zero size ({0, -1}) the range
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* to drop it from consideration at pci_ide_stream_setup() time.
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*/
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struct pci_ide_partner {
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u16 rid_start;
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u16 rid_end;
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u8 stream_index;
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struct pci_bus_region mem_assoc;
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struct pci_bus_region pref_assoc;
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unsigned int default_stream:1;
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unsigned int setup:1;
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unsigned int enable:1;
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};
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/**
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* struct pci_ide_regs - Hardware register association settings for Selective
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* IDE Streams
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* @rid1: IDE RID Association Register 1
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* @rid2: IDE RID Association Register 2
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* @addr: Up to two address association blocks (IDE Address Association Register
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* 1 through 3) for MMIO and prefetchable MMIO
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* @nr_addr: Number of address association blocks initialized
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*
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* See pci_ide_stream_to_regs()
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*/
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struct pci_ide_regs {
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u32 rid1;
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u32 rid2;
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struct {
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u32 assoc1;
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u32 assoc2;
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u32 assoc3;
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} addr[2];
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int nr_addr;
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};
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/**
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* struct pci_ide - PCIe Selective IDE Stream descriptor
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* @pdev: PCIe Endpoint in the pci_ide_partner pair
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* @partner: per-partner settings
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* @host_bridge_stream: allocated from host bridge @ide_stream_ida pool
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* @stream_id: unique Stream ID (within Partner Port pairing)
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* @name: name of the established Selective IDE Stream in sysfs
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* @tsm_dev: For TSM established IDE, the TSM device context
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*
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* Negative @stream_id values indicate "uninitialized" on the
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* expectation that with TSM established IDE the TSM owns the stream_id
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* allocation.
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*/
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struct pci_ide {
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struct pci_dev *pdev;
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struct pci_ide_partner partner[PCI_IDE_PARTNER_MAX];
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u8 host_bridge_stream;
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int stream_id;
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const char *name;
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struct tsm_dev *tsm_dev;
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};
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/*
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* Some devices need help with aliased stream-ids even for idle streams. Use
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* this id as the "never enabled" place holder.
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*/
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#define PCI_IDE_RESERVED_STREAM_ID 255
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void pci_ide_set_nr_streams(struct pci_host_bridge *hb, u16 nr);
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struct pci_ide_partner *pci_ide_to_settings(struct pci_dev *pdev,
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struct pci_ide *ide);
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struct pci_ide *pci_ide_stream_alloc(struct pci_dev *pdev);
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void pci_ide_stream_free(struct pci_ide *ide);
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int pci_ide_stream_register(struct pci_ide *ide);
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void pci_ide_stream_unregister(struct pci_ide *ide);
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void pci_ide_stream_setup(struct pci_dev *pdev, struct pci_ide *ide);
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void pci_ide_stream_teardown(struct pci_dev *pdev, struct pci_ide *ide);
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int pci_ide_stream_enable(struct pci_dev *pdev, struct pci_ide *ide);
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void pci_ide_stream_disable(struct pci_dev *pdev, struct pci_ide *ide);
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void pci_ide_stream_release(struct pci_ide *ide);
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DEFINE_FREE(pci_ide_stream_release, struct pci_ide *, if (_T) pci_ide_stream_release(_T))
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#endif /* __PCI_IDE_H__ */
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