Files
linux/drivers
Zhenyu Wang d110852513 agp/intel: fix cache control for sandybridge
This is broken from 97ef1bdd0b.
Let's set the correct bit for LLC+MLC and LLC only.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-02 10:05:46 +00:00
..
2010-10-26 16:52:08 -07:00
2010-10-26 16:52:14 -07:00
2010-10-25 21:18:19 -04:00