Files
linux/drivers
Thierry Reding d0f02ce3b1 clk: tegra: Fix PLLE programming
PLLE has M, N and P divider shift and width parameters that differ from
the defaults. Furthermore, when clearing the M, N and P divider fields
the corresponding masks were never shifted, thereby clearing only the
lowest bits of the register. This lead to a situation where the PLLE
programming would only work if the register hadn't been touched before.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
2014-04-17 14:12:34 +03:00
..
2014-04-08 21:34:51 +02:00
2014-04-17 14:12:34 +03:00
2014-04-08 13:28:02 +02:00
2014-04-08 13:27:40 +02:00
2014-04-08 13:27:40 +02:00
2014-04-08 12:41:13 -04:00