Rohit Khaire c247c021b1 drm/amdgpu: Fix incorrect register offsets for Sienna Cichlid ...

RLC_CP_SCHEDULERS and RLC_SPARE_INT0 have different
offsets for Sienna Cichlid

Signed-off-by: Rohit Khaire <rohit.khaire@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2021-06-08 14:03:55 -04:00

..

drm

drm/amdgpu: Fix incorrect register offsets for Sienna Cichlid

2021-06-08 14:03:55 -04:00

host1x

gpu: host1x: Split up client initalization and registration

2021-05-17 12:31:05 +02:00

ipu-v3

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trace

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vga

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Makefile

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