周琰杰 (Zhou Yanjie) 34c522a07c MIPS: CI20: Add second percpu timer for SMP. ...

1.Add a new TCU channel as the percpu timer of core1, this is to
  prepare for the subsequent SMP support. The newly added channel
  will not adversely affect the current single-core state.
2.Adjust the position of TCU node to make it consistent with the
  order in jz4780.dtsi file.

Tested-by: Nikolaus Schaller <hns@goldelico.com> # on CI20
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Acked-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

2021-06-30 14:37:16 +02:00

..

ci20.dts

MIPS: CI20: Add second percpu timer for SMP.

2021-06-30 14:37:16 +02:00

cu1000-neo.dts

MIPS: Ingenic: Add missing nodes for Ingenic SoCs and boards.

2020-11-17 21:37:49 +01:00

cu1830-neo.dts

MIPS: Ingenic: Add missing nodes for Ingenic SoCs and boards.

2020-11-17 21:37:49 +01:00

gcw0_proto.dts

MIPS: ingenic: Add support for GCW Zero prototype

2020-05-27 13:04:09 +02:00

gcw0.dts

MIPS: ingenic: gcw0: Set codec to cap-less mode for FM radio

2021-06-01 11:44:47 +02:00

jz4725b.dtsi

MIPS: Ingenic: Add CPU nodes for Ingenic SoCs.

2020-09-21 22:17:38 +02:00

jz4740.dtsi

mips: dts: jz47x: Harmonize EHCI/OHCI DT nodes name

2020-11-12 23:18:23 +01:00

jz4770.dtsi

mips: dts: jz47x: Harmonize EHCI/OHCI DT nodes name

2020-11-12 23:18:23 +01:00

jz4780.dtsi

MIPS: ingenic: jz4780: Fix I2C nodes to match DT doc

2021-06-01 11:44:47 +02:00

Makefile

MIPS: Ingenic: Add YSH & ATIL CU Neo board support.

2020-07-16 10:57:44 +02:00

qi_lb60.dts

MIPS: dts/ingenic: Cleanup qi_lb60.dts

2020-09-07 22:18:24 +02:00

rs90.dts

MIPS: ingenic: rs90: Add dedicated VRAM memory region

2021-06-01 11:44:47 +02:00

x1000.dtsi

MIPS: Ingenic: Add MAC syscon nodes for Ingenic SoCs.

2021-06-30 14:37:16 +02:00

x1830.dtsi

MIPS: Ingenic: Add MAC syscon nodes for Ingenic SoCs.

2021-06-30 14:37:16 +02:00