Paulo Zanoni bb82139b4b drm/i915/icl: compute the combo PHY (DPLL) DP registers ...

Just use the hardcoded tables provided by our spec.

v2: Rebase.
v3: Clarify that 38.4 uses the 19.2 table (James).

Reviewed-by: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180328215803.13835-6-paulo.r.zanoni@intel.com

2018-05-07 16:44:54 -07:00

..

drm

drm/i915/icl: compute the combo PHY (DPLL) DP registers

2018-05-07 16:44:54 -07:00

host1x

gpu: host1x: Use IOMMU groups

2017-12-21 14:52:36 +01:00

ipu-v3

gpu: ipu-v3: prg: avoid possible array underflow

2018-03-15 17:52:08 +01:00

vga

vga_switcheroo: Let HDA autosuspend on mux change

2018-03-13 22:58:49 +01:00

Makefile

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