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e16d0d1672
Create PTL sysfs in xgmi_reset_on_init restore path for MINIMAL_XGMI Signed-off-by: Perry Yuan <perry.yuan@amd.com> Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
65 lines
2.2 KiB
C
65 lines
2.2 KiB
C
/*
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* Copyright 2026 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __AMDGPU_PTL_H__
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#define __AMDGPU_PTL_H__
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enum amdgpu_ptl_fmt {
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AMDGPU_PTL_FMT_I8 = 0,
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AMDGPU_PTL_FMT_F16 = 1,
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AMDGPU_PTL_FMT_BF16 = 2,
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AMDGPU_PTL_FMT_F32 = 3,
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AMDGPU_PTL_FMT_F64 = 4,
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AMDGPU_PTL_FMT_F8 = 5,
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AMDGPU_PTL_FMT_VECTOR = 6,
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AMDGPU_PTL_FMT_INVALID = 7,
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};
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enum amdgpu_ptl_disable_source {
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AMDGPU_PTL_DISABLE_SYSFS = 0,
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AMDGPU_PTL_DISABLE_PROFILER,
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AMDGPU_PTL_DISABLE_MAX,
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};
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struct amdgpu_ptl {
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enum amdgpu_ptl_fmt fmt1;
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enum amdgpu_ptl_fmt fmt2;
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bool enabled;
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bool hw_supported;
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bool permanently_disabled;
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/* PTL disable reference counting */
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atomic_t disable_ref;
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struct mutex mutex;
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DECLARE_BITMAP(disable_bitmap, AMDGPU_PTL_DISABLE_MAX);
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bool ptl_sysfs_created;
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};
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int amdgpu_ptl_perf_monitor_ctrl(struct amdgpu_device *adev, u32 req_code,
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u32 *ptl_state,
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enum amdgpu_ptl_fmt *fmt1,
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enum amdgpu_ptl_fmt *fmt2);
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int amdgpu_ptl_sysfs_init(struct amdgpu_device *adev);
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void amdgpu_ptl_sysfs_fini(struct amdgpu_device *adev);
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extern const struct attribute_group amdgpu_ptl_attr_group;
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#endif /* __AMDGPU_PTL_H__ */
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