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b621908301
Add device tree support for the NXP S32N79 automotive SoC [1]. The S32N79 features eight Arm Cortex-A78AE cores organized in four dual-core clusters, with a three-level cache hierarchy (L1/L2 per core, L3 per dual-core cluster) and 32GB of DRAM memory. It includes an SMMUv3 for IOMMU functionality. On S32N79 SoC, peripherals are organized into subsystems, such as: - CIS (Coherent Interconnect Subsystem) - COSS (Connectivity Subsystem) - FSS (Foundation Subsystem) This initial support includes basic peripherals: - GICv3, SMMUv3 from CIS Subsystem - PL011 UARTs and IRQ steering controller from COSS Subsystem - uSDHC from FSS Subsystem Clock and Pin multiplexing settings for the chip are managed over SCMI. [1] https://www.nxp.com/products/processors-and-microcontrollers/s32-automotive-platform/s32n-vehicle-super-integration-processors:S32N Co-developed-by: Larisa Grigore <larisa.grigore@nxp.com> Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com> Co-developed-by: Andra-Teodora Ilie <andra.ilie@nxp.com> Signed-off-by: Andra-Teodora Ilie <andra.ilie@nxp.com> Co-developed-by: Andrei Cherechesu <andrei.cherechesu@nxp.com> Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>