Hojin Nam 802379b8f9 perf: CXL: fix CPMU filter value mask length ...

CPMU filter value is described as 4B length in CXL r3.0 8.2.7.2.2.
However, it is used as 2B length in code and comments.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Hojin Nam <hj96.nam@samsung.com>
Link: https://lore.kernel.org/r/20240216014522.32321-1-hj96.nam@samsung.com
Signed-off-by: Will Deacon <will@kernel.org>

2024-02-20 12:04:07 +00:00

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amlogic

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arm_cspmu

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hisilicon

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alibaba_uncore_drw_pmu.c

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apple_m1_cpu_pmu.c

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arm_dmc620_pmu.c

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arm_dsu_pmu.c

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arm_pmu_acpi.c

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arm_pmu_platform.c

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arm_pmu.c

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arm_pmuv3.c

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arm_smmuv3_pmu.c

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arm_spe_pmu.c

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arm-cci.c

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arm-ccn.c

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arm-cmn.c

perf/arm-cmn: Workaround AmpereOneX errata AC04_MESH_1 (incorrect child count)

2024-02-09 17:14:04 +00:00

cxl_pmu.c

perf: CXL: fix CPMU filter value mask length

2024-02-20 12:04:07 +00:00

dwc_pcie_pmu.c

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fsl_imx8_ddr_perf.c

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fsl_imx9_ddr_perf.c

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Kconfig

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Makefile

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marvell_cn10k_ddr_pmu.c

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marvell_cn10k_tad_pmu.c

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qcom_l2_pmu.c

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qcom_l3_pmu.c

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riscv_pmu_legacy.c

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riscv_pmu_sbi.c

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riscv_pmu.c

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thunderx2_pmu.c

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xgene_pmu.c

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