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https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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99676aed1f
Currently Nova code uses `&'a Bar0` a lot. This is `&'a Mmio`, where `Mmio` represents an owned MMIO region; this type only exists as a target for `Deref` so `Bar` and `IoMem` can share code and should be avoided to be named directly. The upcoming I/O projection series would make `Io` trait much simpler to implement, and thus the owned MMIO type would be removed in favour of direct `Io` implementation on `Bar` and `IoMem`. Add lifetime parameter to `Bar0<'a>` and change it to be alias of `&'a pci::Bar<'a, ..>`. This also prepares Nova core so that when I/O projection series land, this could be changed to using a MMIO view type directly which avoids double indirection. Signed-off-by: Gary Guo <gary@garyguo.net> Acked-by: Alexandre Courbot <acourbot@nvidia.com> Reviewed-by: Eliot Courtney <ecourtney@nvidia.com> Link: https://patch.msgid.link/20260602170416.2268531-1-gary@kernel.org [ Rebase onto latest drm-rust-next (Blackwell enablement). - Danilo ] Signed-off-by: Danilo Krummrich <dakr@kernel.org>
40 lines
945 B
Rust
40 lines
945 B
Rust
// SPDX-License-Identifier: GPL-2.0
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use core::ops::Range;
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use kernel::{
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dma::DmaMask,
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prelude::*, //
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};
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use crate::{
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driver::Bar0,
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gpu::{
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Architecture,
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Chipset, //
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},
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};
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mod gh100;
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mod tu102;
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pub(crate) trait GpuHal {
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/// Waits for GFW_BOOT completion if required by this hardware family.
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fn wait_gfw_boot_completion(&self, bar: Bar0<'_>) -> Result;
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/// Returns the DMA mask for the current architecture.
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fn dma_mask(&self) -> DmaMask;
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/// Returns the address range of the PCI config mirror space.
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fn pci_config_mirror_range(&self) -> Range<u32>;
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}
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pub(super) fn gpu_hal(chipset: Chipset) -> &'static dyn GpuHal {
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match chipset.arch() {
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Architecture::Turing | Architecture::Ampere | Architecture::Ada => tu102::TU102_HAL,
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Architecture::Hopper | Architecture::BlackwellGB10x | Architecture::BlackwellGB20x => {
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gh100::GH100_HAL
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}
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}
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}
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