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The "pcl818" driver uses an admin-supplied configuration option (`it->options[0]`) to configure the I/O port base address of a board in the PCL-818 series. It currently allows any base address to be configured but the hardware devices only support base addresses (configured by on-board DIP switches) from 0 to 0x3F0 on 16-byte boundaries. If the board has a FIFO and jumper JP6 is in the "Enabled" (default) position, then the base address needs to be on a 32-byte boundary and the length of the I/O port region will be 32 (to allow access to the FIFO registers) instead of 16. The state of jumper JP6 is unknown, so if the board has a FIFO device and is being configured on an odd 16-byte boundary, assume that jumper JP6 is in the "Disabled" position (to disallow access to the FIFO registers). Add a sanity check to ensure the device is not configured at an unsupported base address. If the board has a FIFO and is configured on an odd 16-byte boundary, log a reminder that JP6 needs to be in the "Disabled" position for correct operation. If the board has a FIFO and is configured on an even 16-byte boundary and the configuration option has been set to use the FIFO (`it->options[2] == -1`), log a reminder that JP6 needs to be in the "Enabled" position. Signed-off-by: Ian Abbott <abbotti@mev.co.uk> Link: https://patch.msgid.link/20260130170416.49994-39-abbotti@mev.co.uk Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>