Rex Zhu aa4747c00a drm/amdgpu: refine uvd_4.2 clock gate sequence. ...

1. partial revert commit 91db308d6e96.
   not set uvd bypass mode.
2. enable uvd cg before initialize uvd.
3. set uvd clock to default value 100MHz.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2016-11-11 10:21:04 -05:00

..

acp

drm/amd: add Kconfig dependency for ACP on DRM_AMDGPU

2016-05-25 09:44:15 -04:00

amdgpu

drm/amdgpu: refine uvd_4.2 clock gate sequence.

2016-11-11 10:21:04 -05:00

amdkfd

Merge tag 'v4.8-rc8' into drm-next

2016-09-28 12:08:49 +10:00

include

drm/amdgpu: use same vce state definition in dpm and powerplay

2016-10-25 14:38:39 -04:00

powerplay

drm/amd/powerplay: delete duplicate code in smu7_hwmgr.c

2016-11-11 10:21:03 -05:00

scheduler

Backmerge tag 'v4.9-rc4' into drm-next

2016-11-07 09:37:09 +10:00