Gaurav K Singh aa102d286a drm/i915: MIPI Timings related changes for dual link ...

hactive, hfp, hbp, hsync needs to be halved for dual link MIPI Panels.
Accordingly timing related mmio regs needs to be programmed for both MIPI Ports.

v2: Address review comments by Jani
    - Used a for loop instead of do-while loop

v3: Used for_each_dsi_port macro instead of for loop

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

2014-12-05 15:29:15 +01:00

..

drm

drm/i915: MIPI Timings related changes for dual link

2014-12-05 15:29:15 +01:00

host1x

gpu: host1x: mipi: Set MIPI_CAL_BIAS_PAD_CFG1 register

2014-11-13 16:11:57 +01:00

ipu-v3

Merge tag 'ipu-fixes-3.18' of git://git.pengutronix.de/git/pza/linux into drm-next

2014-10-07 14:31:14 +10:00

vga

Merge branch 'sched-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

2014-10-13 16:23:15 +02:00

Makefile

gpu: ipu-v3: Move i.MX IPUv3 core driver out of staging

2014-06-04 11:06:52 +02:00