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691521a367
The clock controller generates clocks for the whole chip, including
system clocks and all peripheral clocks. This driver support ma35d1
clock gating, divider, and individual PLL configuration.
There are 6 PLLs in ma35d1 SoC:
- CA-PLL for the two Cortex-A35 CPU clock
- SYS-PLL for system bus, which comes from the companion MCU
and cannot be programmed by clock controller.
- DDR-PLL for DDR
- EPLL for GMAC and GFX, Display, and VDEC IPs.
- VPLL for video output pixel clock
- APLL for SDHC, I2S audio, and other IPs.
CA-PLL has only one operation mode.
DDR-PLL, EPLL, VPLL, and APLL are advanced PLLs which have 3
operation modes: integer mode, fraction mode, and spread specturm mode.
Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
20 lines
450 B
Plaintext
20 lines
450 B
Plaintext
# SPDX-License-Identifier: GPL-2.0
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# common clock support for Nuvoton SoC family.
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config COMMON_CLK_NUVOTON
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bool "Nuvoton clock controller common support"
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depends on ARCH_MA35 || COMPILE_TEST
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default y
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help
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Say y here to enable common clock controller for Nuvoton platforms.
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if COMMON_CLK_NUVOTON
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config CLK_MA35D1
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bool "Nuvoton MA35D1 clock controller support"
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default y
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help
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Build the clock controller driver for MA35D1 SoC.
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endif
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