Ben Widawsky a93e41618e drm/i915: generalize pte vs. register BAR allocation ...

All gen6+ parts so far have 1 BAR which holds both the register space
and the GTT PTEs. Up until now, that was a 4MB BAR with half allocated
to each.

I have a strong hunch (wink, nod, wink) that future gens will also keep
a similar 50-50 split though the sizes may change. To help this along
change the code to obey the rule of half the total size instead of a
hard-coded 2MB.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

2013-04-18 09:43:11 +02:00

..

drm

drm/i915: generalize pte vs. register BAR allocation

2013-04-18 09:43:11 +02:00

vga

fbcon: fix locking harder

2013-02-08 12:02:43 +10:00

Makefile

gpu: remove gma500 stub driver

2013-02-20 17:54:58 +10:00