Lucas Stach f513991b69 clk: rockchip: rk3568: Add PLL rate for 724 MHz ...

This rate allows to provide a low-jitter 72,4 MHz pixelclock
for a custom eDP panel from the VPLL.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Link: https://lore.kernel.org/r/20240503153329.3906030-1-l.stach@pengutronix.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

2024-05-04 12:38:13 +02:00

..

clk-cpu.c

clk: rockchip: allow additional mux options for cpu-clock frequency changes

2022-11-14 15:34:18 +01:00

clk-ddr.c

clk: rockchip: Export rockchip_clk_register_ddrclk()

2020-09-22 15:16:37 +02:00

clk-half-divider.c

clk: rockchip: Demote non-conformant kernel-doc header in half-divider

2021-01-26 00:24:05 +01:00

clk-inverter.c

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157

2019-05-30 11:26:37 -07:00

clk-mmc-phase.c

clk: rockchip: Remove an unused field in struct rockchip_mmc_clock

2024-05-04 12:38:02 +02:00

clk-muxgrf.c

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282

2019-06-05 17:36:37 +02:00

clk-pll.c

clk: rockchip: Fix memory leak in rockchip_clk_register_pll()

2022-11-23 14:51:30 +01:00

clk-px30.c

clk: rockchip: support more core div setting

2021-03-21 11:10:58 +01:00

clk-rk3036.c

clk: rockchip: Add support for hclk_sfc on rk3036

2021-07-16 00:33:42 +02:00

clk-rk3128.c

clk: rockchip: rk3128: Fix SCLK_SDMMC's clock name

2023-11-28 10:30:59 +01:00

clk-rk3188.c

clk: rockchip: support more core div setting

2021-03-21 11:10:58 +01:00

clk-rk3228.c

clk: rockchip: support more core div setting

2021-03-21 11:10:58 +01:00

clk-rk3288.c

clk: rockchip: support more core div setting

2021-03-21 11:10:58 +01:00

clk-rk3308.c

clk: rockchip: make rk3308 ddrphy4x clock critical

2021-07-29 12:43:11 +02:00

clk-rk3328.c

clk: rockchip: support more core div setting

2021-03-21 11:10:58 +01:00

clk-rk3368.c

clk: rockchip: support more core div setting

2021-03-21 11:10:58 +01:00

clk-rk3399.c

clk: rockchip: rk3399: Allow to set rate of clk_i2s0_frac's parent

2024-02-27 23:45:53 +01:00

clk-rk3568.c

clk: rockchip: rk3568: Add PLL rate for 724 MHz

2024-05-04 12:38:13 +02:00

clk-rk3588.c

clk: rockchip: rk3588: use linked clock ID for GATE_LINK

2024-02-27 22:23:06 +01:00

clk-rv1108.c

clk: rockchip: support more core div setting

2021-03-21 11:10:58 +01:00

clk-rv1126.c

Merge branches 'clk-versa', 'clk-strdup', 'clk-amlogic', 'clk-allwinner' and 'clk-rockchip' into clk-next

2023-08-30 14:38:19 -07:00

clk.c

clk: rockchip: rk3588: fix CLK_NR_CLKS usage

2024-02-27 17:04:58 +01:00

clk.h

clk: rockchip: rk3588: fix CLK_NR_CLKS usage

2024-02-27 17:04:58 +01:00

Kconfig

clk: rockchip: add clock controller for the RK3588

2022-11-15 11:37:41 +01:00

Makefile

clk: rockchip: add clock controller for the RK3588

2022-11-15 11:37:41 +01:00

rst-rk3588.c

clk: rockchip: rk3588: Add reset line for HDMI Receiver

2024-04-10 07:10:40 +02:00

softrst.c

clk: rockchip: add lookup table support

2022-11-14 15:35:07 +01:00