mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-07-27 21:30:01 -04:00
99676aed1f
Currently Nova code uses `&'a Bar0` a lot. This is `&'a Mmio`, where `Mmio` represents an owned MMIO region; this type only exists as a target for `Deref` so `Bar` and `IoMem` can share code and should be avoided to be named directly. The upcoming I/O projection series would make `Io` trait much simpler to implement, and thus the owned MMIO type would be removed in favour of direct `Io` implementation on `Bar` and `IoMem`. Add lifetime parameter to `Bar0<'a>` and change it to be alias of `&'a pci::Bar<'a, ..>`. This also prepares Nova core so that when I/O projection series land, this could be changed to using a MMIO view type directly which avoids double indirection. Signed-off-by: Gary Guo <gary@garyguo.net> Acked-by: Alexandre Courbot <acourbot@nvidia.com> Reviewed-by: Eliot Courtney <ecourtney@nvidia.com> Link: https://patch.msgid.link/20260602170416.2268531-1-gary@kernel.org [ Rebase onto latest drm-rust-next (Blackwell enablement). - Danilo ] Signed-off-by: Danilo Krummrich <dakr@kernel.org>
102 lines
2.9 KiB
Rust
102 lines
2.9 KiB
Rust
// SPDX-License-Identifier: GPL-2.0
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use kernel::{
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auxiliary,
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device::Core,
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pci,
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pci::{
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Class,
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ClassMask,
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Vendor, //
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},
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prelude::*,
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sizes::SZ_16M,
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sync::atomic::{
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Atomic,
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Relaxed, //
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},
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types::ForLt,
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};
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use crate::gpu::Gpu;
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/// Counter for generating unique auxiliary device IDs.
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static AUXILIARY_ID_COUNTER: Atomic<u32> = Atomic::new(0);
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#[pin_data]
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pub(crate) struct NovaCore<'bound> {
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#[pin]
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pub(crate) gpu: Gpu<'bound>,
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bar: pci::Bar<'bound, BAR0_SIZE>,
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#[allow(clippy::type_complexity)]
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_reg: auxiliary::Registration<'bound, ForLt!(())>,
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}
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pub(crate) struct NovaCoreDriver;
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const BAR0_SIZE: usize = SZ_16M;
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pub(crate) type Bar0<'a> = &'a pci::Bar<'a, BAR0_SIZE>;
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kernel::pci_device_table!(
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PCI_TABLE,
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MODULE_PCI_TABLE,
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<NovaCoreDriver as pci::Driver>::IdInfo,
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[
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// Modern NVIDIA GPUs will show up as either VGA or 3D controllers.
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(
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pci::DeviceId::from_class_and_vendor(
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Class::DISPLAY_VGA,
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ClassMask::ClassSubclass,
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Vendor::NVIDIA
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),
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()
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),
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(
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pci::DeviceId::from_class_and_vendor(
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Class::DISPLAY_3D,
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ClassMask::ClassSubclass,
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Vendor::NVIDIA
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),
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()
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),
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]
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);
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impl pci::Driver for NovaCoreDriver {
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type IdInfo = ();
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type Data<'bound> = NovaCore<'bound>;
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const ID_TABLE: pci::IdTable<Self::IdInfo> = &PCI_TABLE;
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fn probe<'bound>(
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pdev: &'bound pci::Device<Core<'_>>,
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_info: &'bound Self::IdInfo,
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) -> impl PinInit<Self::Data<'bound>, Error> + 'bound {
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pin_init::pin_init_scope(move || {
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dev_dbg!(pdev, "Probe Nova Core GPU driver.\n");
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pdev.enable_device_mem()?;
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pdev.set_master();
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Ok(try_pin_init!(NovaCore {
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bar: pdev.iomap_region_sized::<BAR0_SIZE>(0, c"nova-core/bar0")?,
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// TODO: Use `&bar` self-referential pin-init syntax once available.
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//
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// SAFETY: `bar` is initialized before this expression is evaluated
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// (`try_pin_init!()` initializes fields in declaration order), lives at a pinned
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// stable address, and is dropped after `gpu` (struct field drop order).
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gpu <- Gpu::new(pdev, unsafe { &*core::ptr::from_ref(bar) }),
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_reg: auxiliary::Registration::new(
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pdev.as_ref(),
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c"nova-drm",
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// TODO[XARR]: Use XArray or perhaps IDA for proper ID allocation/recycling. For
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// now, use a simple atomic counter that never recycles IDs.
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AUXILIARY_ID_COUNTER.fetch_add(1, Relaxed),
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crate::MODULE_NAME,
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(),
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)?,
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}))
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})
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}
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}
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