Dillon Varone 9a10c126e0 drm/amd/display: set optimized required for comp buf changes ...

[Description]
When compressed buffer allocation changes, optimized required flag should be
set to trigger an update in optimize bandwidth.

Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Dillon Varone <Dillon.Varone@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2022-12-06 10:17:01 -05:00

..

dcn20_dccg.c

drm/amd/display: Add interface for ADD & DROP PIXEL Registers

2021-06-08 12:22:42 -04:00

dcn20_dccg.h

drm/amd/display: update dccg based on HW delta

2022-09-19 15:16:49 -04:00

dcn20_dpp_cm.c

drm/amd/display: Clean up some inconsistent indenting

2022-07-28 16:05:15 -04:00

dcn20_dpp.c

drm/amd/display: reverted limiting vscsdp_for_colorimetry and ARGB16161616 pixel format addition

2022-08-16 18:07:06 -04:00

dcn20_dpp.h

drm/amd/display: Add DSCL memory low power support

2020-12-01 16:03:40 -05:00

dcn20_dsc.c

drm/amd/display: Enable DCN314 in DC

2022-07-13 20:57:05 -04:00

dcn20_dsc.h

drm/amd/display: Add shift and mask for ICH_RESET_AT_END_OF_LINE

2022-09-19 15:15:57 -04:00

dcn20_dwb_scl.c

drm/amd/display: fix function scopes

2021-12-13 16:34:26 -05:00

dcn20_dwb.c

drm/amd/display: Clean up some inconsistent indenting

2022-07-28 16:05:15 -04:00

dcn20_dwb.h

drm/amd/display: rework macros for DWB register access

2022-11-15 13:35:15 -05:00

dcn20_hubbub.c

drm/amd/display: log additional register state for debug

2021-07-21 13:39:25 -04:00

dcn20_hubbub.h

drm/amd/display: log additional register state for debug

2021-07-21 13:39:25 -04:00

dcn20_hubp.c

drm/amd/display: Fix rotated cursor offset calculation

2022-11-23 09:47:14 -05:00

dcn20_hubp.h

drm/amd/display: Add dependant changes for DCN32/321

2022-06-03 16:43:38 -04:00

dcn20_hwseq.c

drm/amd/display: set optimized required for comp buf changes

2022-12-06 10:17:01 -05:00

dcn20_hwseq.h

drm/amd/display: implement dc_mode_memclk

2021-12-14 16:08:41 -05:00

dcn20_init.c

drm/amd/display: rework recent update PHY state commit

2022-09-19 15:10:24 -04:00

dcn20_init.h

drm/amd/display: cleanup of function pointer tables

2019-11-19 10:12:53 -05:00

dcn20_link_encoder.c

drm/amdgpu/display: restore AUX_DPHY_TX_CONTROL for DCN2.x

2021-04-09 16:38:31 -04:00

dcn20_link_encoder.h

drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3)

2020-11-04 17:11:37 -05:00

dcn20_mmhubbub.c

drm/amd/display: update header files

2022-09-13 12:56:08 -04:00

dcn20_mmhubbub.h

drm/amd/display: rework macros for DWB register access

2022-11-15 13:35:15 -05:00

dcn20_mpc.c

drm/amd/display: Avoid MPC infinite loop

2022-08-10 15:12:06 -04:00

dcn20_mpc.h

drm/amd/display: Use cursor locking to prevent flip delays

2020-04-28 16:19:56 -04:00

dcn20_opp.c

drm/amd/display: Raise DPG height during timing synchronization

2020-10-26 13:29:21 -04:00

dcn20_opp.h

drm/amd/display: Raise DPG height during timing synchronization

2020-10-26 13:29:21 -04:00

dcn20_optc.c

drm/amd/display: Add a missing hook to DCN20

2022-10-10 17:32:55 -04:00

dcn20_optc.h

drm/amd/display: fixed the DSC power off sequence during Driver PnP

2021-11-22 14:45:02 -05:00

dcn20_resource.c

drm/amd/display: rework macros for DWB register access

2022-11-15 13:35:15 -05:00

dcn20_resource.h

drm/amd/display: Add dc_ctx to link_enc_create() parameters

2022-07-25 17:17:28 -04:00

dcn20_stream_encoder.c

drm/amd/display: Program ACP related register

2022-07-05 16:13:18 -04:00

dcn20_stream_encoder.h

drm/amd/display: Add DPCD writes at key points

2021-09-14 15:57:09 -04:00

dcn20_vmid.c

drm/amd/display: Poll for GPUVM context ready (v2)

2019-07-18 14:18:09 -05:00

dcn20_vmid.h

drm/amd/display: rework macros for DWB register access

2022-11-15 13:35:15 -05:00

Makefile

drm/amd/display: move FPU-related code from dcn20 to dml folder

2022-03-15 14:25:16 -04:00