Files
linux/include
Maher Sanalla 8d231dbc3b net/mlx5: Expose shared buffer registers bits and structs
Add the shared receive buffer management and configuration registers:
1. SBPR - Shared Buffer Pools Register
2. SBCM - Shared Buffer Class Management Register

Signed-off-by: Maher Sanalla <msanalla@nvidia.com>
Reviewed-by: Moshe Shemesh <moshe@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2023-01-10 21:24:39 -08:00
..
2022-11-24 23:12:19 +11:00