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synced 2025-12-27 11:06:41 -05:00
6504297872
The VBUS supply regulator is currently assigned to the PHY node.
This causes the VBUS to be always on, even when the controller
needs to be switched to peripheral mode.
Fix the OTG role switching by adding a connector node and moving
the VBUS supply regulator to that node. This way the VBUS gets
correctly switched according to the current role.
Fixes: 946ab10e3f ("arm64: dts: Add support for Kontron OSM-S i.MX8MP SoM and BL carrier board")
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
333 lines
6.7 KiB
Plaintext
333 lines
6.7 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR MIT
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/*
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* Copyright (C) 2022 Kontron Electronics GmbH
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*/
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/dts-v1/;
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#include "imx8mp-kontron-osm-s.dtsi"
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/ {
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model = "Kontron BL i.MX8MP OSM-S";
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compatible = "kontron,imx8mp-bl-osm-s", "kontron,imx8mp-osm-s", "fsl,imx8mp";
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aliases {
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ethernet0 = &fec;
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ethernet1 = &eqos;
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};
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connector {
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compatible = "gpio-usb-b-connector", "usb-b-connector";
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id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
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label = "Type-C";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb1_id>;
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type = "micro";
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vbus-supply = <®_usb1_vbus>;
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port {
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usb_dr_connector: endpoint {
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remote-endpoint = <&usb3_dwc>;
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};
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};
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};
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leds {
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compatible = "gpio-leds";
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led1 {
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label = "led1";
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gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "heartbeat";
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};
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};
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pwm-beeper {
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compatible = "pwm-beeper";
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pwms = <&pwm2 0 5000 0>;
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};
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reg_vcc_panel: regulator-vcc-panel {
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compatible = "regulator-fixed";
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gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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regulator-max-microvolt = <3300000>;
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regulator-min-microvolt = <3300000>;
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regulator-name = "VCC_PANEL";
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};
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};
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&ecspi2 {
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status = "okay";
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eeram@0 {
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compatible = "microchip,48l640";
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reg = <0>;
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spi-max-frequency = <20000000>;
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};
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};
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&eqos { /* Second ethernet (OSM-S ETH_B) */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_eqos_rgmii>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy1>;
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status = "okay";
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mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy1: ethernet-phy@1 {
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compatible = "ethernet-phy-id4f51.e91b";
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reg = <1>;
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pinctrl-0 = <&pinctrl_ethphy1>;
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pinctrl-names = "default";
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reset-assert-us = <10000>;
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reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
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};
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};
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};
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&fec { /* First ethernet (OSM-S ETH_A) */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet_rgmii>;
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phy-connection-type = "rgmii-id";
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phy-handle = <ðphy0>;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@1 {
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compatible = "ethernet-phy-id4f51.e91b";
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reg = <1>;
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pinctrl-0 = <&pinctrl_ethphy0>;
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pinctrl-names = "default";
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reset-assert-us = <10000>;
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reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
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};
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};
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};
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&flexcan1 {
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status = "okay";
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};
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/*
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* Rename SoM signals according to board usage:
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* SDIO_A_PWR_EN -> CAN_ADDR2
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* SDIO_A_WP -> CAN_ADDR3
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*/
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&gpio2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio2>;
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gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", "",
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"SDIO_A_CD", "SDIO_A_CLK", "SDIO_A_CMD", "SDIO_A_D0",
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"SDIO_A_D1", "SDIO_A_D2", "SDIO_A_D3", "CAN_ADDR2",
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"CAN_ADDR3";
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};
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/*
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* Rename SoM signals according to board usage:
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* GPIO_B_0 -> IO_EXP_INT
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* GPIO_B_1 -> IO_EXP_RST
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*/
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&gpio3 {
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gpio-line-names = "PCIE_WAKE", "PCIE_CLKREQ", "PCIE_A_PERST", "SDIO_B_D5",
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"SDIO_B_D6", "SDIO_B_D7", "SPI_A_WP", "SPI_A_HOLD",
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"UART_B_RTS", "UART_B_CTS", "SDIO_B_D0", "SDIO_B_D1",
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"SDIO_B_D2", "SDIO_B_D3", "SDIO_B_WP", "SDIO_B_D4",
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"PCIE_SM_ALERT", "SDIO_B_CLK", "SDIO_B_CMD", "IO_EXP_INT",
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"IO_EXP_RST", "", "BOOT_SEL0", "BOOT_SEL1",
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"", "", "SDIO_B_CD", "SDIO_B_PWR_EN",
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"HDMI_CEC", "HDMI_HPD";
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};
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/*
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* Rename SoM signals according to board usage and remove labels for unsed pins:
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* GPIO_A_6 -> TFT_RESET
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* GPIO_A_7 -> TFT_STBY
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* GPIO_B_3 -> CSI_ENABLE
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* GPIO_B_2 -> USB_HUB_RST
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*/
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&gpio4 {
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gpio-line-names = "", "", "", "",
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"ETH_A_MDC", "ETH_A_MDIO", "ETH_A_RXD0", "ETH_A_RXD1",
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"ETH_A_RXD2", "ETH_A_RXD3", "ETH_A_RX_DV", "ETH_A_RX_CLK",
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"ETH_A_TXD0", "ETH_A_TXD1", "ETH_A_TXD2", "ETH_A_TXD3",
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"ETH_A_TX_EN", "ETH_A_TX_CLK", "CSI_ENABLE", "",
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"USB_HUB_RST", "TFT_RESET", "CAN_A_TX", "UART_A_CTS",
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"UART_A_RTS", "CAN_A_RX", "CAN_B_TX", "CAN_B_RX",
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"TFT_STBY", "CARRIER_PWR_EN", "I2S_A_DATA_IN", "I2S_LRCLK";
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};
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/*
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* Rename SoM signals according to board usage:
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* SPI_A_SDI -> CAN_ADDR0
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* SPI_A_SDO -> CAN_ADDR1
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*/
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&gpio5 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio5>;
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gpio-line-names = "I2S_BITCLK", "I2S_A_DATA_OUT", "I2S_MCLK", "PWM_2",
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"PWM_1", "PWM_0", "SPI_A_SCK", "CAN_ADDR1",
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"CAN_ADDR0", "SPI_A_CS0", "SPI_B_SCK", "SPI_B_SDO",
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"SPI_B_SDI", "SPI_B_CS0", "I2C_A_SCL", "I2C_A_SDA",
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"I2C_B_SCL", "I2C_B_SDA", "PCIE_SMCLK", "PCIE_SMDAT",
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"I2C_CAM_SCL", "I2C_CAM_SDA", "UART_A_RX", "UART_A_TX",
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"UART_C_RX", "UART_C_TX", "UART_CON_RX", "UART_CON_TX",
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"UART_B_RX", "UART_B_TX";
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};
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&hdmi_pvi {
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status = "okay";
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};
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&hdmi_tx {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hdmi>;
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ddc-i2c-bus = <&i2c2>;
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status = "okay";
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};
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&hdmi_tx_phy {
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status = "okay";
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};
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&i2c1 {
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status = "okay";
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gpio_expander_dio: io-expander@20 {
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compatible = "ti,tca6408";
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reg = <0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-line-names = "DIO1_OUT","DIO1_IN", "DIO2_OUT","DIO2_IN",
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"DIO3_OUT","DIO3_IN", "DIO4_OUT","DIO4_IN";
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interrupt-parent = <&gpio3>;
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interrupts = <19 IRQ_TYPE_EDGE_FALLING>;
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reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
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};
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};
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&i2c2 {
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status = "okay";
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};
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&i2c4 {
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status = "okay";
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};
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&lcdif3 {
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status = "okay";
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};
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&pwm2 {
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status = "okay";
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};
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®_usdhc2_vcc {
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status = "disabled";
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};
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&snvs_pwrkey {
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status = "okay";
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};
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&uart1 {
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uart-has-rtscts;
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status = "okay";
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};
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&uart4 {
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linux,rs485-enabled-at-boot-time;
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uart-has-rtscts;
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status = "okay";
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};
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&usb_dwc3_0 {
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adp-disable;
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hnp-disable;
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srp-disable;
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dr_mode = "otg";
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usb-role-switch;
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role-switch-default-mode = "peripheral";
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status = "okay";
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port {
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usb3_dwc: endpoint {
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remote-endpoint = <&usb_dr_connector>;
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};
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};
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};
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&usb_dwc3_1 {
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#address-cells = <1>;
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#size-cells = <0>;
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dr_mode = "host";
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status = "okay";
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usb-hub@1 {
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compatible = "usb424,2514";
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reg = <1>;
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reset-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>;
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};
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};
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&usb3_0 {
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status = "okay";
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};
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&usb3_1 {
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fsl,disable-port-power-control;
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fsl,permanently-attached;
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status = "okay";
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};
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&usb3_phy0 {
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status = "okay";
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};
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&usb3_phy1 {
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status = "okay";
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};
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&usdhc2 {
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pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
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pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
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vmmc-supply = <®_vdd_3v3>;
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status = "okay";
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};
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&iomuxc {
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pinctrl_ethphy0: ethphy0grp {
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fsl,pins = <
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MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x46
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>;
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};
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pinctrl_ethphy1: ethphy1grp {
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fsl,pins = <
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MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x46
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>;
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};
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pinctrl_gpio2: gpio2grp {
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fsl,pins = <
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MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x46
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MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x46
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>;
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};
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pinctrl_gpio5: gpio5grp {
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fsl,pins = <
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MX8MP_IOMUXC_ECSPI1_MOSI__GPIO5_IO07 0x46 /* CAN_ADR0 */
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MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x46 /* CAN_ADR1 */
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>;
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};
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};
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