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https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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7462d18889
Enable user space applications to access the PHC state page when firmware RDMA completion timestamp is supported. This mapping allows user space to convert RDMA completion timestamps to system wall time without kernel transitions, minimizing latency overhead. Applications can directly read the PHC state through mmap, enabling efficient timestamp correlation for precision timing applications. Co-developed-by: Allen Hubbe <allen.hubbe@amd.com> Signed-off-by: Allen Hubbe <allen.hubbe@amd.com> Signed-off-by: Abhijit Gangurde <abhijit.gangurde@amd.com> Link: https://patch.msgid.link/20260610154216.712374-4-abhijit.gangurde@amd.com Signed-off-by: Leon Romanovsky <leon@kernel.org>
117 lines
1.8 KiB
C
117 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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/* Copyright (C) 2018-2025, Advanced Micro Devices, Inc */
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#ifndef IONIC_ABI_H
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#define IONIC_ABI_H
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#include <linux/types.h>
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#define IONIC_ABI_VERSION 1
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#define IONIC_EXPDB_64 1
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#define IONIC_EXPDB_128 2
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#define IONIC_EXPDB_256 4
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#define IONIC_EXPDB_512 8
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#define IONIC_EXPDB_SQ 1
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#define IONIC_EXPDB_RQ 2
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#define IONIC_CMB_ENABLE 1
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#define IONIC_CMB_REQUIRE 2
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#define IONIC_CMB_EXPDB 4
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#define IONIC_CMB_WC 8
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#define IONIC_CMB_UC 16
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struct ionic_ctx_req {
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__u32 rsvd[2];
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};
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struct ionic_ctx_resp {
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__u32 rsvd;
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__u32 page_shift;
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__aligned_u64 dbell_offset;
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__u16 version;
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__u8 qp_opcodes;
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__u8 admin_opcodes;
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__u8 sq_qtype;
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__u8 rq_qtype;
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__u8 cq_qtype;
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__u8 admin_qtype;
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__u8 max_stride;
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__u8 max_spec;
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__u8 udma_count;
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__u8 expdb_mask;
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__u8 expdb_qtypes;
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__u8 rsvd2[3];
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__aligned_u64 phc_offset;
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};
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struct ionic_qdesc {
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__aligned_u64 addr;
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__u32 size;
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__u16 mask;
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__u8 depth_log2;
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__u8 stride_log2;
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};
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struct ionic_ah_resp {
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__u32 ahid;
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__u32 pad;
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};
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struct ionic_cq_req {
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struct ionic_qdesc cq[2];
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__u8 udma_mask;
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__u8 rsvd[7];
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};
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struct ionic_cq_resp {
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__u32 cqid[2];
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__u8 udma_mask;
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__u8 rsvd[7];
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};
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struct ionic_qp_req {
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struct ionic_qdesc sq;
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struct ionic_qdesc rq;
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__u8 sq_spec;
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__u8 rq_spec;
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__u8 sq_cmb;
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__u8 rq_cmb;
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__u8 udma_mask;
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__u8 rsvd[3];
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};
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struct ionic_qp_resp {
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__u32 qpid;
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__u8 sq_cmb;
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__u8 rq_cmb;
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__u8 udma_idx;
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__u8 rsvd[1];
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__aligned_u64 sq_cmb_offset;
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__aligned_u64 rq_cmb_offset;
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};
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struct ionic_srq_req {
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struct ionic_qdesc rq;
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__u8 rq_spec;
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__u8 rq_cmb;
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__u8 udma_mask;
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__u8 rsvd[5];
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};
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struct ionic_srq_resp {
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__u32 qpid;
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__u8 rq_cmb;
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__u8 udma_idx;
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__u8 rsvd[2];
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__aligned_u64 rq_cmb_offset;
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};
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#endif /* IONIC_ABI_H */
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