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16e6a1a3cb
Pull phy updates from Vinod Koul:
"As usual bunch of new device and driver support and updates to
existing drivers and addition of Manivannan to help with reviews.
New Support:
- Mediatek MT8196 DSI PHY support
- Renesas RZ/G3L usb2 support
- Qualcomm SM8475 QMP USB PHY and PCIe phy, IPQ9650 QMP PCIe PHY,
QUSB2 Phy for Shikra SoC, Hawi support for QMP PCIe phy and UFS
PHY. Glymur QMP PCIe Multi-PHY driver and multiple link-mode
support, ipq5210 PCIe phy support
- Spacemit USB3/PCIe comb PHY driver
Updates:
- Samsung hdptx driver improvements for modernizing the register
access and code cleanup
- Qualcomm drop duplicate v8 DP headers, improved runtime handling
for qmp drivers
- Rockchip clock lane phase tuning and 2500 Mbps support and TMDS
rate handling
- Freescale imx8mq improvements for runtime pm, pd handling"
* tag 'phy-for-7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (76 commits)
MAINTAINERS: Add Manivannan Sadhasivam as the Reviewer for Generic PHY Framework
phy: rockchip-samsung-dcphy: fix out-of-range max_register
phy: qcom: qmp-pcie: Add QMP PCIe Multi-PHY driver
dt-bindings: phy: qcom: Add Glymur QMP PCIe multiple link-mode PHY
phy: rockchip: samsung-hdptx: Consistently use bitfield macros
phy: rockchip: samsung-hdptx: Simplify GRF access with FIELD_PREP_WM16()
phy: rockchip: samsung-hdptx: Drop restrict_rate_change handling
phy: rockchip: samsung-hdptx: Consolidate consumer_put on error path
phy: rockchip: samsung-hdptx: Drop TMDS rate setup workaround
phy: rockchip: samsung-hdptx: Handle uncommitted PHY config changes
phy: rockchip: samsung-hdptx: Fix rate recalculation for 3.2GHz FRL
phy: rockchip: samsung-hdptx: Guard against clk rate integer underflow
phy: rockchip: samsung-hdptx: Prevent divide-by-zero when computing clk rate
phy: rockchip: samsung-hdptx: Fix rate recalculation for high bpc
phy: qcom: qmp-combo: Drop qmp_v4_calibrate_dp_phy
phy: qcom: qmp-combo: Correct pre-emphasis table for QMP v4 DP PHYs
phy: renesas: rcar-gen3-usb2: Ignore missing VBUS regulator
phy: qcom: qmp-pcie: Add support for SM8475 Gen3x1 PCIe0 port
phy: qcom: qmp-pcie: Add pcs_lane1 offset to V5 offsets
dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add SM8475 QMP PHY
...