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99b98993ae
Add LPCLK clock handling to the RZ/G2L MIPI DSI driver to support proper DSI timing parameter configuration on RZ/V2H SoCs. While lpclk is present on both RZ/G2L and RZ/V2H SoCs, the RZ/V2H SoC specifically uses the lpclk rate to configure the DSI timing parameter ULPSEXIT. Introduce a new lpclk field in the rzg2l_mipi_dsi structure and acquire the "lpclk" clock during probe to enable lpclk rate-based timing calculations on RZ/V2H while maintaining compatibility with RZ/G2L. Co-developed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://patch.msgid.link/20251015192611.241920-7-prabhakar.mahadev-lad.rj@bp.renesas.com