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99b48ecc8e800983b6e00a2350daaeceba1f7406
linux/drivers/gpu/drm/amd/display/dc/dcn30
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Nicholas Kazlauskas e2f60fd8ba drm/amd/display: Add missing DCN30 registers and fields for OTG_CRC_CNTL2 
[Why]
When enabling the debugfs for CRC capture we hit assertions caused by
register address and field masks and shifts missing.

[How]
We want these registers programmed, so add in the SRI/SF entries for
this register.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-14 14:38:17 -04:00
..
dcn30_afmt.c
drm/amd/display: Add DCN3 AFMT
2020-07-01 01:59:15 -04:00
dcn30_afmt.h
drm/amd/display: Add DCN3 AFMT
2020-07-01 01:59:15 -04:00
dcn30_cm_common.c
drm/amd/display: Add DCN3 DPP
2020-07-01 01:59:14 -04:00
dcn30_cm_common.h
drm/amd/display: Add DCN3 DPP
2020-07-01 01:59:14 -04:00
dcn30_dccg.c
drm/amd/display: Add DCN3 DCCG
2020-07-01 01:59:14 -04:00
dcn30_dccg.h
drm/amd/display: Add DCN3 DCCG
2020-07-01 01:59:14 -04:00
dcn30_dio_link_encoder.c
…
dcn30_dio_link_encoder.h
…
dcn30_dio_stream_encoder.c
…
dcn30_dio_stream_encoder.h
drm/amd/display: Add missing reg mask for dcn3
2020-07-08 09:02:37 -04:00
dcn30_dpp_cm.c
drm/amd/display: Add DCN3 DPP
2020-07-01 01:59:14 -04:00
dcn30_dpp.c
drm/amd/display: Add DCN3 DPP
2020-07-01 01:59:14 -04:00
dcn30_dpp.h
drm/amd/display: Add DCN3 DPP
2020-07-01 01:59:14 -04:00
dcn30_dwb_cm.c
drm/amd/display: Add DCN3 DWB
2020-07-01 01:59:14 -04:00
dcn30_dwb.c
drm/amd/display: Add DCN3 DWB
2020-07-01 01:59:14 -04:00
dcn30_dwb.h
drm/amd/display: Add DCN3 DWB
2020-07-01 01:59:14 -04:00
dcn30_hubbub.c
drm/amd/display: Add DCN3 HUBHUB
2020-07-01 01:59:14 -04:00
dcn30_hubbub.h
drm/amd/display: Add DCN3 HUBHUB
2020-07-01 01:59:14 -04:00
dcn30_hubp.c
drm/amd/display: Add DCN3 HUBP
2020-07-01 01:59:14 -04:00
dcn30_hubp.h
drm/amd/display: Add DCN3 HUBP
2020-07-01 01:59:14 -04:00
dcn30_hwseq.c
drm/amd/display: enable seamless boot for dcn30
2020-07-01 01:59:26 -04:00
dcn30_hwseq.h
drm/amd/display: Add DCN3 HWSEQ
2020-07-01 01:59:15 -04:00
dcn30_init.c
drm/amd/display: enable seamless boot for dcn30
2020-07-01 01:59:26 -04:00
dcn30_init.h
drm/amd/display: Init function tables for DCN3
2020-07-01 01:59:15 -04:00
dcn30_mmhubbub.c
drm/amd/display: Add DCN3 MMHUBHUB
2020-07-01 01:59:14 -04:00
dcn30_mmhubbub.h
drm/amd/display: Add DCN3 MMHUBHUB
2020-07-01 01:59:14 -04:00
dcn30_mpc.c
drm/amd/display: Add DCN3 MPC
2020-07-01 01:59:14 -04:00
dcn30_mpc.h
drm/amd/display: Add DCN3 MPC
2020-07-01 01:59:14 -04:00
dcn30_opp.h
drm/amd/display: Add DCN3 OPP header
2020-07-01 01:59:14 -04:00
dcn30_optc.c
drm/amd/display: Add DCN3 OPTC
2020-07-01 01:59:14 -04:00
dcn30_optc.h
drm/amd/display: Add missing DCN30 registers and fields for OTG_CRC_CNTL2
2020-07-14 14:38:17 -04:00
dcn30_resource.c
drm/amd/display: fix dcn3 p_state_change_support validation (v2)
2020-07-14 14:37:33 -04:00
dcn30_resource.h
drm/amd/display: Add DCN3 Resource
2020-07-01 01:59:15 -04:00
dcn30_vpg.c
drm/amd/display: Add DCN3 VPG
2020-07-01 01:59:15 -04:00
dcn30_vpg.h
drm/amd/display: Add DCN3 VPG
2020-07-01 01:59:15 -04:00
Makefile
drm/amd/display: Add DCN3 blocks to Makefile
2020-07-01 01:59:15 -04:00