mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-05-28 14:16:36 -04:00
2c9b351240
Pull kvm updates from Paolo Bonzini:
"ARM:
- Initial infrastructure for shadow stage-2 MMUs, as part of nested
virtualization enablement
- Support for userspace changes to the guest CTR_EL0 value, enabling
(in part) migration of VMs between heterogenous hardware
- Fixes + improvements to pKVM's FF-A proxy, adding support for v1.1
of the protocol
- FPSIMD/SVE support for nested, including merged trap configuration
and exception routing
- New command-line parameter to control the WFx trap behavior under
KVM
- Introduce kCFI hardening in the EL2 hypervisor
- Fixes + cleanups for handling presence/absence of FEAT_TCRX
- Miscellaneous fixes + documentation updates
LoongArch:
- Add paravirt steal time support
- Add support for KVM_DIRTY_LOG_INITIALLY_SET
- Add perf kvm-stat support for loongarch
RISC-V:
- Redirect AMO load/store access fault traps to guest
- perf kvm stat support
- Use guest files for IMSIC virtualization, when available
s390:
- Assortment of tiny fixes which are not time critical
x86:
- Fixes for Xen emulation
- Add a global struct to consolidate tracking of host values, e.g.
EFER
- Add KVM_CAP_X86_APIC_BUS_CYCLES_NS to allow configuring the
effective APIC bus frequency, because TDX
- Print the name of the APICv/AVIC inhibits in the relevant
tracepoint
- Clean up KVM's handling of vendor specific emulation to
consistently act on "compatible with Intel/AMD", versus checking
for a specific vendor
- Drop MTRR virtualization, and instead always honor guest PAT on
CPUs that support self-snoop
- Update to the newfangled Intel CPU FMS infrastructure
- Don't advertise IA32_PERF_GLOBAL_OVF_CTRL as an MSR-to-be-saved, as
it reads '0' and writes from userspace are ignored
- Misc cleanups
x86 - MMU:
- Small cleanups, renames and refactoring extracted from the upcoming
Intel TDX support
- Don't allocate kvm_mmu_page.shadowed_translation for shadow pages
that can't hold leafs SPTEs
- Unconditionally drop mmu_lock when allocating TDP MMU page tables
for eager page splitting, to avoid stalling vCPUs when splitting
huge pages
- Bug the VM instead of simply warning if KVM tries to split a SPTE
that is non-present or not-huge. KVM is guaranteed to end up in a
broken state because the callers fully expect a valid SPTE, it's
all but dangerous to let more MMU changes happen afterwards
x86 - AMD:
- Make per-CPU save_area allocations NUMA-aware
- Force sev_es_host_save_area() to be inlined to avoid calling into
an instrumentable function from noinstr code
- Base support for running SEV-SNP guests. API-wise, this includes a
new KVM_X86_SNP_VM type, encrypting/measure the initial image into
guest memory, and finalizing it before launching it. Internally,
there are some gmem/mmu hooks needed to prepare gmem-allocated
pages before mapping them into guest private memory ranges
This includes basic support for attestation guest requests, enough
to say that KVM supports the GHCB 2.0 specification
There is no support yet for loading into the firmware those signing
keys to be used for attestation requests, and therefore no need yet
for the host to provide certificate data for those keys.
To support fetching certificate data from userspace, a new KVM exit
type will be needed to handle fetching the certificate from
userspace.
An attempt to define a new KVM_EXIT_COCO / KVM_EXIT_COCO_REQ_CERTS
exit type to handle this was introduced in v1 of this patchset, but
is still being discussed by community, so for now this patchset
only implements a stub version of SNP Extended Guest Requests that
does not provide certificate data
x86 - Intel:
- Remove an unnecessary EPT TLB flush when enabling hardware
- Fix a series of bugs that cause KVM to fail to detect nested
pending posted interrupts as valid wake eents for a vCPU executing
HLT in L2 (with HLT-exiting disable by L1)
- KVM: x86: Suppress MMIO that is triggered during task switch
emulation
Explicitly suppress userspace emulated MMIO exits that are
triggered when emulating a task switch as KVM doesn't support
userspace MMIO during complex (multi-step) emulation
Silently ignoring the exit request can result in the
WARN_ON_ONCE(vcpu->mmio_needed) firing if KVM exits to userspace
for some other reason prior to purging mmio_needed
See commit 0dc902267c ("KVM: x86: Suppress pending MMIO write
exits if emulator detects exception") for more details on KVM's
limitations with respect to emulated MMIO during complex emulator
flows
Generic:
- Rename the AS_UNMOVABLE flag that was introduced for KVM to
AS_INACCESSIBLE, because the special casing needed by these pages
is not due to just unmovability (and in fact they are only
unmovable because the CPU cannot access them)
- New ioctl to populate the KVM page tables in advance, which is
useful to mitigate KVM page faults during guest boot or after live
migration. The code will also be used by TDX, but (probably) not
through the ioctl
- Enable halt poll shrinking by default, as Intel found it to be a
clear win
- Setup empty IRQ routing when creating a VM to avoid having to
synchronize SRCU when creating a split IRQCHIP on x86
- Rework the sched_in/out() paths to replace kvm_arch_sched_in() with
a flag that arch code can use for hooking both sched_in() and
sched_out()
- Take the vCPU @id as an "unsigned long" instead of "u32" to avoid
truncating a bogus value from userspace, e.g. to help userspace
detect bugs
- Mark a vCPU as preempted if and only if it's scheduled out while in
the KVM_RUN loop, e.g. to avoid marking it preempted and thus
writing guest memory when retrieving guest state during live
migration blackout
Selftests:
- Remove dead code in the memslot modification stress test
- Treat "branch instructions retired" as supported on all AMD Family
17h+ CPUs
- Print the guest pseudo-RNG seed only when it changes, to avoid
spamming the log for tests that create lots of VMs
- Make the PMU counters test less flaky when counting LLC cache
misses by doing CLFLUSH{OPT} in every loop iteration"
* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (227 commits)
crypto: ccp: Add the SNP_VLEK_LOAD command
KVM: x86/pmu: Add kvm_pmu_call() to simplify static calls of kvm_pmu_ops
KVM: x86: Introduce kvm_x86_call() to simplify static calls of kvm_x86_ops
KVM: x86: Replace static_call_cond() with static_call()
KVM: SEV: Provide support for SNP_EXTENDED_GUEST_REQUEST NAE event
x86/sev: Move sev_guest.h into common SEV header
KVM: SEV: Provide support for SNP_GUEST_REQUEST NAE event
KVM: x86: Suppress MMIO that is triggered during task switch emulation
KVM: x86/mmu: Clean up make_huge_page_split_spte() definition and intro
KVM: x86/mmu: Bug the VM if KVM tries to split a !hugepage SPTE
KVM: selftests: x86: Add test for KVM_PRE_FAULT_MEMORY
KVM: x86: Implement kvm_arch_vcpu_pre_fault_memory()
KVM: x86/mmu: Make kvm_mmu_do_page_fault() return mapped level
KVM: x86/mmu: Account pf_{fixed,emulate,spurious} in callers of "do page fault"
KVM: x86/mmu: Bump pf_taken stat only in the "real" page fault handler
KVM: Add KVM_PRE_FAULT_MEMORY vcpu ioctl to pre-populate guest memory
KVM: Document KVM_PRE_FAULT_MEMORY ioctl
mm, virt: merge AS_UNMOVABLE and AS_INACCESSIBLE
perf kvm: Add kvm-stat for loongarch64
LoongArch: KVM: Add PV steal time support in guest side
...
456 lines
16 KiB
C
456 lines
16 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2013 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*/
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#ifndef __ASM_ESR_H
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#define __ASM_ESR_H
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#include <asm/memory.h>
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#include <asm/sysreg.h>
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#define ESR_ELx_EC_UNKNOWN (0x00)
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#define ESR_ELx_EC_WFx (0x01)
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/* Unallocated EC: 0x02 */
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#define ESR_ELx_EC_CP15_32 (0x03)
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#define ESR_ELx_EC_CP15_64 (0x04)
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#define ESR_ELx_EC_CP14_MR (0x05)
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#define ESR_ELx_EC_CP14_LS (0x06)
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#define ESR_ELx_EC_FP_ASIMD (0x07)
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#define ESR_ELx_EC_CP10_ID (0x08) /* EL2 only */
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#define ESR_ELx_EC_PAC (0x09) /* EL2 and above */
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/* Unallocated EC: 0x0A - 0x0B */
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#define ESR_ELx_EC_CP14_64 (0x0C)
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#define ESR_ELx_EC_BTI (0x0D)
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#define ESR_ELx_EC_ILL (0x0E)
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/* Unallocated EC: 0x0F - 0x10 */
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#define ESR_ELx_EC_SVC32 (0x11)
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#define ESR_ELx_EC_HVC32 (0x12) /* EL2 only */
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#define ESR_ELx_EC_SMC32 (0x13) /* EL2 and above */
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/* Unallocated EC: 0x14 */
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#define ESR_ELx_EC_SVC64 (0x15)
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#define ESR_ELx_EC_HVC64 (0x16) /* EL2 and above */
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#define ESR_ELx_EC_SMC64 (0x17) /* EL2 and above */
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#define ESR_ELx_EC_SYS64 (0x18)
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#define ESR_ELx_EC_SVE (0x19)
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#define ESR_ELx_EC_ERET (0x1a) /* EL2 only */
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/* Unallocated EC: 0x1B */
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#define ESR_ELx_EC_FPAC (0x1C) /* EL1 and above */
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#define ESR_ELx_EC_SME (0x1D)
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/* Unallocated EC: 0x1E */
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#define ESR_ELx_EC_IMP_DEF (0x1f) /* EL3 only */
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#define ESR_ELx_EC_IABT_LOW (0x20)
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#define ESR_ELx_EC_IABT_CUR (0x21)
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#define ESR_ELx_EC_PC_ALIGN (0x22)
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/* Unallocated EC: 0x23 */
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#define ESR_ELx_EC_DABT_LOW (0x24)
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#define ESR_ELx_EC_DABT_CUR (0x25)
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#define ESR_ELx_EC_SP_ALIGN (0x26)
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#define ESR_ELx_EC_MOPS (0x27)
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#define ESR_ELx_EC_FP_EXC32 (0x28)
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/* Unallocated EC: 0x29 - 0x2B */
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#define ESR_ELx_EC_FP_EXC64 (0x2C)
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/* Unallocated EC: 0x2D - 0x2E */
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#define ESR_ELx_EC_SERROR (0x2F)
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#define ESR_ELx_EC_BREAKPT_LOW (0x30)
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#define ESR_ELx_EC_BREAKPT_CUR (0x31)
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#define ESR_ELx_EC_SOFTSTP_LOW (0x32)
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#define ESR_ELx_EC_SOFTSTP_CUR (0x33)
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#define ESR_ELx_EC_WATCHPT_LOW (0x34)
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#define ESR_ELx_EC_WATCHPT_CUR (0x35)
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/* Unallocated EC: 0x36 - 0x37 */
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#define ESR_ELx_EC_BKPT32 (0x38)
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/* Unallocated EC: 0x39 */
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#define ESR_ELx_EC_VECTOR32 (0x3A) /* EL2 only */
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/* Unallocated EC: 0x3B */
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#define ESR_ELx_EC_BRK64 (0x3C)
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/* Unallocated EC: 0x3D - 0x3F */
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#define ESR_ELx_EC_MAX (0x3F)
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#define ESR_ELx_EC_SHIFT (26)
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#define ESR_ELx_EC_WIDTH (6)
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#define ESR_ELx_EC_MASK (UL(0x3F) << ESR_ELx_EC_SHIFT)
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#define ESR_ELx_EC(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT)
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#define ESR_ELx_IL_SHIFT (25)
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#define ESR_ELx_IL (UL(1) << ESR_ELx_IL_SHIFT)
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#define ESR_ELx_ISS_MASK (GENMASK(24, 0))
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#define ESR_ELx_ISS(esr) ((esr) & ESR_ELx_ISS_MASK)
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#define ESR_ELx_ISS2_SHIFT (32)
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#define ESR_ELx_ISS2_MASK (GENMASK_ULL(55, 32))
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#define ESR_ELx_ISS2(esr) (((esr) & ESR_ELx_ISS2_MASK) >> ESR_ELx_ISS2_SHIFT)
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/* ISS field definitions shared by different classes */
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#define ESR_ELx_WNR_SHIFT (6)
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#define ESR_ELx_WNR (UL(1) << ESR_ELx_WNR_SHIFT)
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/* Asynchronous Error Type */
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#define ESR_ELx_IDS_SHIFT (24)
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#define ESR_ELx_IDS (UL(1) << ESR_ELx_IDS_SHIFT)
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#define ESR_ELx_AET_SHIFT (10)
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#define ESR_ELx_AET (UL(0x7) << ESR_ELx_AET_SHIFT)
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#define ESR_ELx_AET_UC (UL(0) << ESR_ELx_AET_SHIFT)
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#define ESR_ELx_AET_UEU (UL(1) << ESR_ELx_AET_SHIFT)
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#define ESR_ELx_AET_UEO (UL(2) << ESR_ELx_AET_SHIFT)
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#define ESR_ELx_AET_UER (UL(3) << ESR_ELx_AET_SHIFT)
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#define ESR_ELx_AET_CE (UL(6) << ESR_ELx_AET_SHIFT)
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/* Shared ISS field definitions for Data/Instruction aborts */
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#define ESR_ELx_SET_SHIFT (11)
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#define ESR_ELx_SET_MASK (UL(3) << ESR_ELx_SET_SHIFT)
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#define ESR_ELx_FnV_SHIFT (10)
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#define ESR_ELx_FnV (UL(1) << ESR_ELx_FnV_SHIFT)
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#define ESR_ELx_EA_SHIFT (9)
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#define ESR_ELx_EA (UL(1) << ESR_ELx_EA_SHIFT)
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#define ESR_ELx_S1PTW_SHIFT (7)
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#define ESR_ELx_S1PTW (UL(1) << ESR_ELx_S1PTW_SHIFT)
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/* Shared ISS fault status code(IFSC/DFSC) for Data/Instruction aborts */
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#define ESR_ELx_FSC (0x3F)
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#define ESR_ELx_FSC_TYPE (0x3C)
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#define ESR_ELx_FSC_LEVEL (0x03)
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#define ESR_ELx_FSC_EXTABT (0x10)
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#define ESR_ELx_FSC_MTE (0x11)
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#define ESR_ELx_FSC_SERROR (0x11)
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#define ESR_ELx_FSC_ACCESS (0x08)
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#define ESR_ELx_FSC_FAULT (0x04)
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#define ESR_ELx_FSC_PERM (0x0C)
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#define ESR_ELx_FSC_SEA_TTW(n) (0x14 + (n))
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#define ESR_ELx_FSC_SECC (0x18)
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#define ESR_ELx_FSC_SECC_TTW(n) (0x1c + (n))
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/* Status codes for individual page table levels */
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#define ESR_ELx_FSC_ACCESS_L(n) (ESR_ELx_FSC_ACCESS + n)
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#define ESR_ELx_FSC_PERM_L(n) (ESR_ELx_FSC_PERM + n)
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#define ESR_ELx_FSC_FAULT_nL (0x2C)
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#define ESR_ELx_FSC_FAULT_L(n) (((n) < 0 ? ESR_ELx_FSC_FAULT_nL : \
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ESR_ELx_FSC_FAULT) + (n))
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/* ISS field definitions for Data Aborts */
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#define ESR_ELx_ISV_SHIFT (24)
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#define ESR_ELx_ISV (UL(1) << ESR_ELx_ISV_SHIFT)
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#define ESR_ELx_SAS_SHIFT (22)
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#define ESR_ELx_SAS (UL(3) << ESR_ELx_SAS_SHIFT)
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#define ESR_ELx_SSE_SHIFT (21)
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#define ESR_ELx_SSE (UL(1) << ESR_ELx_SSE_SHIFT)
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#define ESR_ELx_SRT_SHIFT (16)
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#define ESR_ELx_SRT_MASK (UL(0x1F) << ESR_ELx_SRT_SHIFT)
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#define ESR_ELx_SF_SHIFT (15)
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#define ESR_ELx_SF (UL(1) << ESR_ELx_SF_SHIFT)
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#define ESR_ELx_AR_SHIFT (14)
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#define ESR_ELx_AR (UL(1) << ESR_ELx_AR_SHIFT)
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#define ESR_ELx_CM_SHIFT (8)
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#define ESR_ELx_CM (UL(1) << ESR_ELx_CM_SHIFT)
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/* ISS2 field definitions for Data Aborts */
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#define ESR_ELx_TnD_SHIFT (10)
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#define ESR_ELx_TnD (UL(1) << ESR_ELx_TnD_SHIFT)
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#define ESR_ELx_TagAccess_SHIFT (9)
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#define ESR_ELx_TagAccess (UL(1) << ESR_ELx_TagAccess_SHIFT)
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#define ESR_ELx_GCS_SHIFT (8)
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#define ESR_ELx_GCS (UL(1) << ESR_ELx_GCS_SHIFT)
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#define ESR_ELx_Overlay_SHIFT (6)
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#define ESR_ELx_Overlay (UL(1) << ESR_ELx_Overlay_SHIFT)
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#define ESR_ELx_DirtyBit_SHIFT (5)
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#define ESR_ELx_DirtyBit (UL(1) << ESR_ELx_DirtyBit_SHIFT)
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#define ESR_ELx_Xs_SHIFT (0)
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#define ESR_ELx_Xs_MASK (GENMASK_ULL(4, 0))
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/* ISS field definitions for exceptions taken in to Hyp */
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#define ESR_ELx_FSC_ADDRSZ (0x00)
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#define ESR_ELx_CV (UL(1) << 24)
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#define ESR_ELx_COND_SHIFT (20)
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#define ESR_ELx_COND_MASK (UL(0xF) << ESR_ELx_COND_SHIFT)
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#define ESR_ELx_WFx_ISS_RN (UL(0x1F) << 5)
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#define ESR_ELx_WFx_ISS_RV (UL(1) << 2)
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#define ESR_ELx_WFx_ISS_TI (UL(3) << 0)
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#define ESR_ELx_WFx_ISS_WFxT (UL(2) << 0)
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#define ESR_ELx_WFx_ISS_WFI (UL(0) << 0)
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#define ESR_ELx_WFx_ISS_WFE (UL(1) << 0)
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#define ESR_ELx_xVC_IMM_MASK ((UL(1) << 16) - 1)
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#define DISR_EL1_IDS (UL(1) << 24)
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/*
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* DISR_EL1 and ESR_ELx share the bottom 13 bits, but the RES0 bits may mean
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* different things in the future...
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*/
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#define DISR_EL1_ESR_MASK (ESR_ELx_AET | ESR_ELx_EA | ESR_ELx_FSC)
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/* ESR value templates for specific events */
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#define ESR_ELx_WFx_MASK (ESR_ELx_EC_MASK | \
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(ESR_ELx_WFx_ISS_TI & ~ESR_ELx_WFx_ISS_WFxT))
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#define ESR_ELx_WFx_WFI_VAL ((ESR_ELx_EC_WFx << ESR_ELx_EC_SHIFT) | \
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ESR_ELx_WFx_ISS_WFI)
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/* BRK instruction trap from AArch64 state */
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#define ESR_ELx_BRK64_ISS_COMMENT_MASK 0xffff
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/* ISS field definitions for System instruction traps */
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#define ESR_ELx_SYS64_ISS_RES0_SHIFT 22
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#define ESR_ELx_SYS64_ISS_RES0_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT)
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#define ESR_ELx_SYS64_ISS_DIR_MASK 0x1
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#define ESR_ELx_SYS64_ISS_DIR_READ 0x1
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#define ESR_ELx_SYS64_ISS_DIR_WRITE 0x0
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#define ESR_ELx_SYS64_ISS_RT_SHIFT 5
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#define ESR_ELx_SYS64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_SYS64_ISS_RT_SHIFT)
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#define ESR_ELx_SYS64_ISS_CRM_SHIFT 1
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#define ESR_ELx_SYS64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRM_SHIFT)
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#define ESR_ELx_SYS64_ISS_CRN_SHIFT 10
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#define ESR_ELx_SYS64_ISS_CRN_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRN_SHIFT)
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#define ESR_ELx_SYS64_ISS_OP1_SHIFT 14
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#define ESR_ELx_SYS64_ISS_OP1_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP1_SHIFT)
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#define ESR_ELx_SYS64_ISS_OP2_SHIFT 17
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#define ESR_ELx_SYS64_ISS_OP2_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP2_SHIFT)
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#define ESR_ELx_SYS64_ISS_OP0_SHIFT 20
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#define ESR_ELx_SYS64_ISS_OP0_MASK (UL(0x3) << ESR_ELx_SYS64_ISS_OP0_SHIFT)
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#define ESR_ELx_SYS64_ISS_SYS_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \
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ESR_ELx_SYS64_ISS_OP1_MASK | \
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ESR_ELx_SYS64_ISS_OP2_MASK | \
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ESR_ELx_SYS64_ISS_CRN_MASK | \
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ESR_ELx_SYS64_ISS_CRM_MASK)
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#define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \
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(((op0) << ESR_ELx_SYS64_ISS_OP0_SHIFT) | \
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((op1) << ESR_ELx_SYS64_ISS_OP1_SHIFT) | \
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((op2) << ESR_ELx_SYS64_ISS_OP2_SHIFT) | \
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((crn) << ESR_ELx_SYS64_ISS_CRN_SHIFT) | \
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((crm) << ESR_ELx_SYS64_ISS_CRM_SHIFT))
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#define ESR_ELx_SYS64_ISS_SYS_OP_MASK (ESR_ELx_SYS64_ISS_SYS_MASK | \
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ESR_ELx_SYS64_ISS_DIR_MASK)
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#define ESR_ELx_SYS64_ISS_RT(esr) \
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(((esr) & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT)
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/*
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* User space cache operations have the following sysreg encoding
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* in System instructions.
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* op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 13, 14 }, WRITE (L=0)
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*/
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#define ESR_ELx_SYS64_ISS_CRM_DC_CIVAC 14
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#define ESR_ELx_SYS64_ISS_CRM_DC_CVADP 13
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#define ESR_ELx_SYS64_ISS_CRM_DC_CVAP 12
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#define ESR_ELx_SYS64_ISS_CRM_DC_CVAU 11
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#define ESR_ELx_SYS64_ISS_CRM_DC_CVAC 10
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#define ESR_ELx_SYS64_ISS_CRM_IC_IVAU 5
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#define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \
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ESR_ELx_SYS64_ISS_OP1_MASK | \
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ESR_ELx_SYS64_ISS_OP2_MASK | \
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ESR_ELx_SYS64_ISS_CRN_MASK | \
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ESR_ELx_SYS64_ISS_DIR_MASK)
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#define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL \
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(ESR_ELx_SYS64_ISS_SYS_VAL(1, 3, 1, 7, 0) | \
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ESR_ELx_SYS64_ISS_DIR_WRITE)
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/*
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* User space MRS operations which are supported for emulation
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* have the following sysreg encoding in System instructions.
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* op0 = 3, op1= 0, crn = 0, {crm = 0, 4-7}, READ (L = 1)
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*/
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#define ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \
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ESR_ELx_SYS64_ISS_OP1_MASK | \
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ESR_ELx_SYS64_ISS_CRN_MASK | \
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ESR_ELx_SYS64_ISS_DIR_MASK)
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#define ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL \
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(ESR_ELx_SYS64_ISS_SYS_VAL(3, 0, 0, 0, 0) | \
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ESR_ELx_SYS64_ISS_DIR_READ)
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#define ESR_ELx_SYS64_ISS_SYS_CTR ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 1, 0, 0)
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#define ESR_ELx_SYS64_ISS_SYS_CTR_READ (ESR_ELx_SYS64_ISS_SYS_CTR | \
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ESR_ELx_SYS64_ISS_DIR_READ)
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#define ESR_ELx_SYS64_ISS_SYS_CNTVCT (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) | \
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ESR_ELx_SYS64_ISS_DIR_READ)
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#define ESR_ELx_SYS64_ISS_SYS_CNTVCTSS (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 6, 14, 0) | \
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ESR_ELx_SYS64_ISS_DIR_READ)
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#define ESR_ELx_SYS64_ISS_SYS_CNTFRQ (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 0, 14, 0) | \
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ESR_ELx_SYS64_ISS_DIR_READ)
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#define esr_sys64_to_sysreg(e) \
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sys_reg((((e) & ESR_ELx_SYS64_ISS_OP0_MASK) >> \
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ESR_ELx_SYS64_ISS_OP0_SHIFT), \
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(((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \
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ESR_ELx_SYS64_ISS_OP1_SHIFT), \
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(((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \
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ESR_ELx_SYS64_ISS_CRN_SHIFT), \
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(((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \
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ESR_ELx_SYS64_ISS_CRM_SHIFT), \
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(((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \
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ESR_ELx_SYS64_ISS_OP2_SHIFT))
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|
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#define esr_cp15_to_sysreg(e) \
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sys_reg(3, \
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(((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \
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ESR_ELx_SYS64_ISS_OP1_SHIFT), \
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(((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \
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ESR_ELx_SYS64_ISS_CRN_SHIFT), \
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(((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \
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ESR_ELx_SYS64_ISS_CRM_SHIFT), \
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(((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \
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ESR_ELx_SYS64_ISS_OP2_SHIFT))
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|
|
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/* ISS field definitions for ERET/ERETAA/ERETAB trapping */
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#define ESR_ELx_ERET_ISS_ERET 0x2
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#define ESR_ELx_ERET_ISS_ERETA 0x1
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/*
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|
* ISS field definitions for floating-point exception traps
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* (FP_EXC_32/FP_EXC_64).
|
|
*
|
|
* (The FPEXC_* constants are used instead for common bits.)
|
|
*/
|
|
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#define ESR_ELx_FP_EXC_TFV (UL(1) << 23)
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|
|
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/*
|
|
* ISS field definitions for CP15 accesses
|
|
*/
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|
#define ESR_ELx_CP15_32_ISS_DIR_MASK 0x1
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#define ESR_ELx_CP15_32_ISS_DIR_READ 0x1
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#define ESR_ELx_CP15_32_ISS_DIR_WRITE 0x0
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|
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#define ESR_ELx_CP15_32_ISS_RT_SHIFT 5
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#define ESR_ELx_CP15_32_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_32_ISS_RT_SHIFT)
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|
#define ESR_ELx_CP15_32_ISS_CRM_SHIFT 1
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#define ESR_ELx_CP15_32_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRM_SHIFT)
|
|
#define ESR_ELx_CP15_32_ISS_CRN_SHIFT 10
|
|
#define ESR_ELx_CP15_32_ISS_CRN_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRN_SHIFT)
|
|
#define ESR_ELx_CP15_32_ISS_OP1_SHIFT 14
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|
#define ESR_ELx_CP15_32_ISS_OP1_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP1_SHIFT)
|
|
#define ESR_ELx_CP15_32_ISS_OP2_SHIFT 17
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|
#define ESR_ELx_CP15_32_ISS_OP2_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP2_SHIFT)
|
|
|
|
#define ESR_ELx_CP15_32_ISS_SYS_MASK (ESR_ELx_CP15_32_ISS_OP1_MASK | \
|
|
ESR_ELx_CP15_32_ISS_OP2_MASK | \
|
|
ESR_ELx_CP15_32_ISS_CRN_MASK | \
|
|
ESR_ELx_CP15_32_ISS_CRM_MASK | \
|
|
ESR_ELx_CP15_32_ISS_DIR_MASK)
|
|
#define ESR_ELx_CP15_32_ISS_SYS_VAL(op1, op2, crn, crm) \
|
|
(((op1) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) | \
|
|
((op2) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) | \
|
|
((crn) << ESR_ELx_CP15_32_ISS_CRN_SHIFT) | \
|
|
((crm) << ESR_ELx_CP15_32_ISS_CRM_SHIFT))
|
|
|
|
#define ESR_ELx_CP15_64_ISS_DIR_MASK 0x1
|
|
#define ESR_ELx_CP15_64_ISS_DIR_READ 0x1
|
|
#define ESR_ELx_CP15_64_ISS_DIR_WRITE 0x0
|
|
|
|
#define ESR_ELx_CP15_64_ISS_RT_SHIFT 5
|
|
#define ESR_ELx_CP15_64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT_SHIFT)
|
|
|
|
#define ESR_ELx_CP15_64_ISS_RT2_SHIFT 10
|
|
#define ESR_ELx_CP15_64_ISS_RT2_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT2_SHIFT)
|
|
|
|
#define ESR_ELx_CP15_64_ISS_OP1_SHIFT 16
|
|
#define ESR_ELx_CP15_64_ISS_OP1_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_OP1_SHIFT)
|
|
#define ESR_ELx_CP15_64_ISS_CRM_SHIFT 1
|
|
#define ESR_ELx_CP15_64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_CRM_SHIFT)
|
|
|
|
#define ESR_ELx_CP15_64_ISS_SYS_VAL(op1, crm) \
|
|
(((op1) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) | \
|
|
((crm) << ESR_ELx_CP15_64_ISS_CRM_SHIFT))
|
|
|
|
#define ESR_ELx_CP15_64_ISS_SYS_MASK (ESR_ELx_CP15_64_ISS_OP1_MASK | \
|
|
ESR_ELx_CP15_64_ISS_CRM_MASK | \
|
|
ESR_ELx_CP15_64_ISS_DIR_MASK)
|
|
|
|
#define ESR_ELx_CP15_64_ISS_SYS_CNTVCT (ESR_ELx_CP15_64_ISS_SYS_VAL(1, 14) | \
|
|
ESR_ELx_CP15_64_ISS_DIR_READ)
|
|
|
|
#define ESR_ELx_CP15_64_ISS_SYS_CNTVCTSS (ESR_ELx_CP15_64_ISS_SYS_VAL(9, 14) | \
|
|
ESR_ELx_CP15_64_ISS_DIR_READ)
|
|
|
|
#define ESR_ELx_CP15_32_ISS_SYS_CNTFRQ (ESR_ELx_CP15_32_ISS_SYS_VAL(0, 0, 14, 0) |\
|
|
ESR_ELx_CP15_32_ISS_DIR_READ)
|
|
|
|
/*
|
|
* ISS values for SME traps
|
|
*/
|
|
|
|
#define ESR_ELx_SME_ISS_SME_DISABLED 0
|
|
#define ESR_ELx_SME_ISS_ILL 1
|
|
#define ESR_ELx_SME_ISS_SM_DISABLED 2
|
|
#define ESR_ELx_SME_ISS_ZA_DISABLED 3
|
|
#define ESR_ELx_SME_ISS_ZT_DISABLED 4
|
|
|
|
/* ISS field definitions for MOPS exceptions */
|
|
#define ESR_ELx_MOPS_ISS_MEM_INST (UL(1) << 24)
|
|
#define ESR_ELx_MOPS_ISS_FROM_EPILOGUE (UL(1) << 18)
|
|
#define ESR_ELx_MOPS_ISS_WRONG_OPTION (UL(1) << 17)
|
|
#define ESR_ELx_MOPS_ISS_OPTION_A (UL(1) << 16)
|
|
#define ESR_ELx_MOPS_ISS_DESTREG(esr) (((esr) & (UL(0x1f) << 10)) >> 10)
|
|
#define ESR_ELx_MOPS_ISS_SRCREG(esr) (((esr) & (UL(0x1f) << 5)) >> 5)
|
|
#define ESR_ELx_MOPS_ISS_SIZEREG(esr) (((esr) & (UL(0x1f) << 0)) >> 0)
|
|
|
|
#ifndef __ASSEMBLY__
|
|
#include <asm/types.h>
|
|
|
|
static inline unsigned long esr_brk_comment(unsigned long esr)
|
|
{
|
|
return esr & ESR_ELx_BRK64_ISS_COMMENT_MASK;
|
|
}
|
|
|
|
static inline bool esr_is_data_abort(unsigned long esr)
|
|
{
|
|
const unsigned long ec = ESR_ELx_EC(esr);
|
|
|
|
return ec == ESR_ELx_EC_DABT_LOW || ec == ESR_ELx_EC_DABT_CUR;
|
|
}
|
|
|
|
static inline bool esr_is_cfi_brk(unsigned long esr)
|
|
{
|
|
return ESR_ELx_EC(esr) == ESR_ELx_EC_BRK64 &&
|
|
(esr_brk_comment(esr) & ~CFI_BRK_IMM_MASK) == CFI_BRK_IMM_BASE;
|
|
}
|
|
|
|
static inline bool esr_fsc_is_translation_fault(unsigned long esr)
|
|
{
|
|
esr = esr & ESR_ELx_FSC;
|
|
|
|
return (esr == ESR_ELx_FSC_FAULT_L(3)) ||
|
|
(esr == ESR_ELx_FSC_FAULT_L(2)) ||
|
|
(esr == ESR_ELx_FSC_FAULT_L(1)) ||
|
|
(esr == ESR_ELx_FSC_FAULT_L(0)) ||
|
|
(esr == ESR_ELx_FSC_FAULT_L(-1));
|
|
}
|
|
|
|
static inline bool esr_fsc_is_permission_fault(unsigned long esr)
|
|
{
|
|
esr = esr & ESR_ELx_FSC;
|
|
|
|
return (esr == ESR_ELx_FSC_PERM_L(3)) ||
|
|
(esr == ESR_ELx_FSC_PERM_L(2)) ||
|
|
(esr == ESR_ELx_FSC_PERM_L(1)) ||
|
|
(esr == ESR_ELx_FSC_PERM_L(0));
|
|
}
|
|
|
|
static inline bool esr_fsc_is_access_flag_fault(unsigned long esr)
|
|
{
|
|
esr = esr & ESR_ELx_FSC;
|
|
|
|
return (esr == ESR_ELx_FSC_ACCESS_L(3)) ||
|
|
(esr == ESR_ELx_FSC_ACCESS_L(2)) ||
|
|
(esr == ESR_ELx_FSC_ACCESS_L(1)) ||
|
|
(esr == ESR_ELx_FSC_ACCESS_L(0));
|
|
}
|
|
|
|
/* Indicate whether ESR.EC==0x1A is for an ERETAx instruction */
|
|
static inline bool esr_iss_is_eretax(unsigned long esr)
|
|
{
|
|
return esr & ESR_ELx_ERET_ISS_ERET;
|
|
}
|
|
|
|
/* Indicate which key is used for ERETAx (false: A-Key, true: B-Key) */
|
|
static inline bool esr_iss_is_eretab(unsigned long esr)
|
|
{
|
|
return esr & ESR_ELx_ERET_ISS_ERETA;
|
|
}
|
|
|
|
const char *esr_get_class_string(unsigned long esr);
|
|
#endif /* __ASSEMBLY */
|
|
|
|
#endif /* __ASM_ESR_H */
|