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49625c6e4d
The control register for TWSI8 clocks, APBC_TWSI8_CLK_RST, contains mux selection bits, reset assertion bit and enable bits for function and bus clocks. It has a quirk that reading always results in zero. As a workaround, let's hardcode the mux value as zero to select pll1_d78_31p5 as parent and treat twsi8_clk as a gate, whose enable mask is combined from the real bus and function clocks to avoid the write-only register being shared between two clk_hws, in which case updates of one clk_hw zero the other's bits. With a 1:1 factor serving as placeholder for the bus clock, the I2C-8 controller could be brought up, which is essential for boards attaching power-management chips to it. Signed-off-by: Haylen Chu <heylenay@4d2.org> Reviewed-by: Alex Elder <elder@riscstar.com> Reviewed-by: Yixun Lan <dlan@gentoo.org> Link: https://lore.kernel.org/r/20250416135406.16284-5-heylenay@4d2.org Signed-off-by: Yixun Lan <dlan@gentoo.org>