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WCL has 3 pipes and two TC ports, create power well mapping to reflect HW. Rest remains similar to Xe3 power well configuration. v2: Remove TC3/4 ports as they do not exist. Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Link: https://lore.kernel.org/r/20250808081931.4101388-1-chaitanya.kumar.borah@intel.com Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>