Files
linux/drivers/gpu/drm/amd/display/dmub/src
Nicholas Kazlauskas 4b0b4c17f5 drm/amd/display: Reset DMUB mailbox SW state after HW reset
[Why]
Otherwise we can be out of sync with what's in the hardware, leading
to us rerunning every command that's presently in the ringbuffer.

[How]
Reset software state for the mailboxes in hw_reset callback.
This is already done as part of the mailbox init in hw_init, but we
do need to remember to reset the last cached wptr value as well here.

Reviewed-by: Hansen Dsouza <hansen.dsouza@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-01-31 14:03:36 -05:00
..
2020-11-16 12:17:43 -05:00
2020-11-16 12:17:43 -05:00
2022-02-18 14:07:01 -05:00
2022-02-18 14:07:01 -05:00