Yihan Zhu 86f955b793 drm/amd/display: update sequential pg logic DCN35 ...

[WHY & HOW]
No check for HUBP/DPP power gating when DSC instance is still running. Avoid HUBP/DPP to
power gate when corresponding DSC block is still running in the power gating calculation.

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Duncan Ma <duncan.ma@amd.com>
Signed-off-by: Yihan Zhu <Yihan.Zhu@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2025-01-06 14:44:26 -05:00

..

drm

drm/amd/display: update sequential pg logic DCN35

2025-01-06 14:44:26 -05:00

host1x

gpu: host1x: Set up device DMA parameters

2024-10-15 18:46:25 +02:00

ipu-v3

Merge tag 'driver-core-6.11-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core

2024-07-25 10:42:22 -07:00

trace

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vga

drm: Do delayed switcheroo in drm_lastclose()

2024-08-13 16:21:07 +02:00

Makefile

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