Ben Widawsky 8693607ae4 drm/i915: No LLC_MLC for HSW. ...

The mid-level cache or as it's more commonly referred to now as L3, is
not setup this way on HSW.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

2012-11-11 23:51:09 +01:00

..

drm

drm/i915: No LLC_MLC for HSW.

2012-11-11 23:51:09 +01:00

stub

i915: select VIDEO_OUTPUT_CONTROL for ACPI_VIDEO

2011-04-13 09:10:25 +10:00

vga

Merge branch 'pci/yinghai-misc' into next

2012-09-24 17:24:11 -06:00

Makefile

gpu: Add Intel GMA500(Poulsbo) Stub Driver

2010-10-26 11:00:13 +10:00