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Linear Address Space Separation (LASS) is a security feature that mitigates a class of side-channel attacks relying on speculative access across the user/kernel boundary. Privilege mode based access protection already exists today with paging and features such as SMEP and SMAP. However, to enforce these protections, the processor must traverse the paging structures in memory. An attacker can use timing information resulting from this traversal to determine details about the paging structures, and to determine the layout of the kernel memory. LASS provides the same mode-based protections as paging but without traversing the paging structures. Because the protections are enforced prior to page-walks, an attacker will not be able to derive paging-based timing information from the various caching structures such as the TLBs, mid-level caches, page walker, data caches, etc. LASS enforcement relies on the kernel implementation to divide the 64-bit virtual address space into two halves: Addr[63]=0 -> User address space Addr[63]=1 -> Kernel address space Any data access or code execution across address spaces typically results in a #GP fault, with an #SS generated in some rare cases. The LASS enforcement for kernel data accesses is dependent on CR4.SMAP being set. The enforcement can be disabled by toggling the RFLAGS.AC bit similar to SMAP. Define the CPU feature bits to enumerate LASS. Also, disable the feature at compile time on 32-bit kernels. Use a direct dependency on X86_32 (instead of !X86_64) to make it easier to combine with similar 32-bit specific dependencies in the future. LASS mitigates a class of side-channel speculative attacks, such as Spectre LAM, described in the paper, "Leaky Address Masking: Exploiting Unmasked Spectre Gadgets with Noncanonical Address Translation". Add the "lass" flag to /proc/cpuinfo to indicate that the feature is supported by hardware and enabled by the kernel. This allows userspace to determine if the system is secure against such attacks. Signed-off-by: Sohil Mehta <sohil.mehta@intel.com> Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> Reviewed-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Xin Li (Intel) <xin@zytor.com> Reviewed-by: Dave Hansen <dave.hansen@linux.intel.com> Link: https://patch.msgid.link/20251118182911.2983253-2-sohil.mehta%40intel.com
184 lines
7.3 KiB
C
184 lines
7.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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#ifndef _UAPI_ASM_X86_PROCESSOR_FLAGS_H
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#define _UAPI_ASM_X86_PROCESSOR_FLAGS_H
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/* Various flags defined: can be included from assembler. */
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#include <linux/const.h>
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/*
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* EFLAGS bits
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*/
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#define X86_EFLAGS_CF_BIT 0 /* Carry Flag */
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#define X86_EFLAGS_CF _BITUL(X86_EFLAGS_CF_BIT)
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#define X86_EFLAGS_FIXED_BIT 1 /* Bit 1 - always on */
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#define X86_EFLAGS_FIXED _BITUL(X86_EFLAGS_FIXED_BIT)
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#define X86_EFLAGS_PF_BIT 2 /* Parity Flag */
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#define X86_EFLAGS_PF _BITUL(X86_EFLAGS_PF_BIT)
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#define X86_EFLAGS_AF_BIT 4 /* Auxiliary carry Flag */
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#define X86_EFLAGS_AF _BITUL(X86_EFLAGS_AF_BIT)
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#define X86_EFLAGS_ZF_BIT 6 /* Zero Flag */
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#define X86_EFLAGS_ZF _BITUL(X86_EFLAGS_ZF_BIT)
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#define X86_EFLAGS_SF_BIT 7 /* Sign Flag */
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#define X86_EFLAGS_SF _BITUL(X86_EFLAGS_SF_BIT)
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#define X86_EFLAGS_TF_BIT 8 /* Trap Flag */
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#define X86_EFLAGS_TF _BITUL(X86_EFLAGS_TF_BIT)
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#define X86_EFLAGS_IF_BIT 9 /* Interrupt Flag */
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#define X86_EFLAGS_IF _BITUL(X86_EFLAGS_IF_BIT)
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#define X86_EFLAGS_DF_BIT 10 /* Direction Flag */
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#define X86_EFLAGS_DF _BITUL(X86_EFLAGS_DF_BIT)
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#define X86_EFLAGS_OF_BIT 11 /* Overflow Flag */
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#define X86_EFLAGS_OF _BITUL(X86_EFLAGS_OF_BIT)
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#define X86_EFLAGS_IOPL_BIT 12 /* I/O Privilege Level (2 bits) */
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#define X86_EFLAGS_IOPL (_AC(3,UL) << X86_EFLAGS_IOPL_BIT)
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#define X86_EFLAGS_NT_BIT 14 /* Nested Task */
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#define X86_EFLAGS_NT _BITUL(X86_EFLAGS_NT_BIT)
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#define X86_EFLAGS_RF_BIT 16 /* Resume Flag */
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#define X86_EFLAGS_RF _BITUL(X86_EFLAGS_RF_BIT)
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#define X86_EFLAGS_VM_BIT 17 /* Virtual Mode */
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#define X86_EFLAGS_VM _BITUL(X86_EFLAGS_VM_BIT)
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#define X86_EFLAGS_AC_BIT 18 /* Alignment Check/Access Control */
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#define X86_EFLAGS_AC _BITUL(X86_EFLAGS_AC_BIT)
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#define X86_EFLAGS_VIF_BIT 19 /* Virtual Interrupt Flag */
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#define X86_EFLAGS_VIF _BITUL(X86_EFLAGS_VIF_BIT)
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#define X86_EFLAGS_VIP_BIT 20 /* Virtual Interrupt Pending */
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#define X86_EFLAGS_VIP _BITUL(X86_EFLAGS_VIP_BIT)
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#define X86_EFLAGS_ID_BIT 21 /* CPUID detection */
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#define X86_EFLAGS_ID _BITUL(X86_EFLAGS_ID_BIT)
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/*
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* Basic CPU control in CR0
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*/
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#define X86_CR0_PE_BIT 0 /* Protection Enable */
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#define X86_CR0_PE _BITUL(X86_CR0_PE_BIT)
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#define X86_CR0_MP_BIT 1 /* Monitor Coprocessor */
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#define X86_CR0_MP _BITUL(X86_CR0_MP_BIT)
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#define X86_CR0_EM_BIT 2 /* Emulation */
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#define X86_CR0_EM _BITUL(X86_CR0_EM_BIT)
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#define X86_CR0_TS_BIT 3 /* Task Switched */
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#define X86_CR0_TS _BITUL(X86_CR0_TS_BIT)
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#define X86_CR0_ET_BIT 4 /* Extension Type */
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#define X86_CR0_ET _BITUL(X86_CR0_ET_BIT)
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#define X86_CR0_NE_BIT 5 /* Numeric Error */
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#define X86_CR0_NE _BITUL(X86_CR0_NE_BIT)
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#define X86_CR0_WP_BIT 16 /* Write Protect */
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#define X86_CR0_WP _BITUL(X86_CR0_WP_BIT)
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#define X86_CR0_AM_BIT 18 /* Alignment Mask */
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#define X86_CR0_AM _BITUL(X86_CR0_AM_BIT)
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#define X86_CR0_NW_BIT 29 /* Not Write-through */
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#define X86_CR0_NW _BITUL(X86_CR0_NW_BIT)
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#define X86_CR0_CD_BIT 30 /* Cache Disable */
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#define X86_CR0_CD _BITUL(X86_CR0_CD_BIT)
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#define X86_CR0_PG_BIT 31 /* Paging */
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#define X86_CR0_PG _BITUL(X86_CR0_PG_BIT)
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/*
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* Paging options in CR3
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*/
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#define X86_CR3_PWT_BIT 3 /* Page Write Through */
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#define X86_CR3_PWT _BITUL(X86_CR3_PWT_BIT)
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#define X86_CR3_PCD_BIT 4 /* Page Cache Disable */
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#define X86_CR3_PCD _BITUL(X86_CR3_PCD_BIT)
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#define X86_CR3_PCID_BITS 12
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#define X86_CR3_PCID_MASK (_AC((1UL << X86_CR3_PCID_BITS) - 1, UL))
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#define X86_CR3_LAM_U57_BIT 61 /* Activate LAM for userspace, 62:57 bits masked */
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#define X86_CR3_LAM_U57 _BITULL(X86_CR3_LAM_U57_BIT)
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#define X86_CR3_LAM_U48_BIT 62 /* Activate LAM for userspace, 62:48 bits masked */
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#define X86_CR3_LAM_U48 _BITULL(X86_CR3_LAM_U48_BIT)
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#define X86_CR3_PCID_NOFLUSH_BIT 63 /* Preserve old PCID */
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#define X86_CR3_PCID_NOFLUSH _BITULL(X86_CR3_PCID_NOFLUSH_BIT)
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/*
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* Intel CPU features in CR4
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*/
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#define X86_CR4_VME_BIT 0 /* enable vm86 extensions */
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#define X86_CR4_VME _BITUL(X86_CR4_VME_BIT)
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#define X86_CR4_PVI_BIT 1 /* virtual interrupts flag enable */
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#define X86_CR4_PVI _BITUL(X86_CR4_PVI_BIT)
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#define X86_CR4_TSD_BIT 2 /* disable time stamp at ipl 3 */
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#define X86_CR4_TSD _BITUL(X86_CR4_TSD_BIT)
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#define X86_CR4_DE_BIT 3 /* enable debugging extensions */
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#define X86_CR4_DE _BITUL(X86_CR4_DE_BIT)
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#define X86_CR4_PSE_BIT 4 /* enable page size extensions */
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#define X86_CR4_PSE _BITUL(X86_CR4_PSE_BIT)
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#define X86_CR4_PAE_BIT 5 /* enable physical address extensions */
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#define X86_CR4_PAE _BITUL(X86_CR4_PAE_BIT)
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#define X86_CR4_MCE_BIT 6 /* Machine check enable */
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#define X86_CR4_MCE _BITUL(X86_CR4_MCE_BIT)
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#define X86_CR4_PGE_BIT 7 /* enable global pages */
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#define X86_CR4_PGE _BITUL(X86_CR4_PGE_BIT)
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#define X86_CR4_PCE_BIT 8 /* enable performance counters at ipl 3 */
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#define X86_CR4_PCE _BITUL(X86_CR4_PCE_BIT)
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#define X86_CR4_OSFXSR_BIT 9 /* enable fast FPU save and restore */
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#define X86_CR4_OSFXSR _BITUL(X86_CR4_OSFXSR_BIT)
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#define X86_CR4_OSXMMEXCPT_BIT 10 /* enable unmasked SSE exceptions */
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#define X86_CR4_OSXMMEXCPT _BITUL(X86_CR4_OSXMMEXCPT_BIT)
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#define X86_CR4_UMIP_BIT 11 /* enable UMIP support */
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#define X86_CR4_UMIP _BITUL(X86_CR4_UMIP_BIT)
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#define X86_CR4_LA57_BIT 12 /* enable 5-level page tables */
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#define X86_CR4_LA57 _BITUL(X86_CR4_LA57_BIT)
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#define X86_CR4_VMXE_BIT 13 /* enable VMX virtualization */
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#define X86_CR4_VMXE _BITUL(X86_CR4_VMXE_BIT)
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#define X86_CR4_SMXE_BIT 14 /* enable safer mode (TXT) */
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#define X86_CR4_SMXE _BITUL(X86_CR4_SMXE_BIT)
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#define X86_CR4_FSGSBASE_BIT 16 /* enable RDWRFSGS support */
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#define X86_CR4_FSGSBASE _BITUL(X86_CR4_FSGSBASE_BIT)
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#define X86_CR4_PCIDE_BIT 17 /* enable PCID support */
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#define X86_CR4_PCIDE _BITUL(X86_CR4_PCIDE_BIT)
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#define X86_CR4_OSXSAVE_BIT 18 /* enable xsave and xrestore */
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#define X86_CR4_OSXSAVE _BITUL(X86_CR4_OSXSAVE_BIT)
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#define X86_CR4_SMEP_BIT 20 /* enable SMEP support */
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#define X86_CR4_SMEP _BITUL(X86_CR4_SMEP_BIT)
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#define X86_CR4_SMAP_BIT 21 /* enable SMAP support */
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#define X86_CR4_SMAP _BITUL(X86_CR4_SMAP_BIT)
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#define X86_CR4_PKE_BIT 22 /* enable Protection Keys support */
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#define X86_CR4_PKE _BITUL(X86_CR4_PKE_BIT)
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#define X86_CR4_CET_BIT 23 /* enable Control-flow Enforcement Technology */
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#define X86_CR4_CET _BITUL(X86_CR4_CET_BIT)
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#define X86_CR4_LASS_BIT 27 /* enable Linear Address Space Separation support */
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#define X86_CR4_LASS _BITUL(X86_CR4_LASS_BIT)
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#define X86_CR4_LAM_SUP_BIT 28 /* LAM for supervisor pointers */
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#define X86_CR4_LAM_SUP _BITUL(X86_CR4_LAM_SUP_BIT)
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#ifdef __x86_64__
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#define X86_CR4_FRED_BIT 32 /* enable FRED kernel entry */
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#define X86_CR4_FRED _BITUL(X86_CR4_FRED_BIT)
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#else
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#define X86_CR4_FRED (0)
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#endif
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/*
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* x86-64 Task Priority Register, CR8
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*/
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#define X86_CR8_TPR _AC(0x0000000f,UL) /* task priority register */
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/*
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* AMD and Transmeta use MSRs for configuration; see <asm/msr-index.h>
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*/
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/*
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* NSC/Cyrix CPU configuration register indexes
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*/
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#define CX86_PCR0 0x20
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#define CX86_GCR 0xb8
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#define CX86_CCR0 0xc0
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#define CX86_CCR1 0xc1
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#define CX86_CCR2 0xc2
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#define CX86_CCR3 0xc3
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#define CX86_CCR4 0xe8
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#define CX86_CCR5 0xe9
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#define CX86_CCR6 0xea
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#define CX86_CCR7 0xeb
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#define CX86_PCR1 0xf0
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#define CX86_DIR0 0xfe
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#define CX86_DIR1 0xff
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#define CX86_ARR_BASE 0xc4
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#define CX86_RCR_BASE 0xdc
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#define CR0_STATE (X86_CR0_PE | X86_CR0_MP | X86_CR0_ET | \
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X86_CR0_NE | X86_CR0_WP | X86_CR0_AM | \
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X86_CR0_PG)
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#endif /* _UAPI_ASM_X86_PROCESSOR_FLAGS_H */
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