Krzysztof Kozlowski 0699018b41 drm/msm/dsi/phy: Define PHY_CMN_CLK_CFG[01] bitfields and simplify saving ...

Add bitfields for PHY_CMN_CLK_CFG0 and PHY_CMN_CLK_CFG1 registers to
avoid hard-coding bit masks and shifts and make the code a bit more
readable.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/638324/
Link: https://lore.kernel.org/r/20250219-drm-msm-phy-pll-cfg-reg-v5-2-d28973fa513a@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

2025-02-26 12:15:49 +02:00

..

phy

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dsi_cfg.c

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dsi_cfg.h

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dsi_host.c

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dsi_manager.c

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dsi.c

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dsi.h

…