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3b5d43245f
Add CXL Features support. Setup code for enabling in kernel usage of CXL Features. Expecting EDAC/RAS to utilize CXL Features in kernel for things such as memory sparing. Also prepartion for enabling of CXL FWCTL support to issue allowed Features from user space.
23 lines
590 B
Makefile
23 lines
590 B
Makefile
# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_CXL_BUS) += cxl_core.o
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obj-$(CONFIG_CXL_SUSPEND) += suspend.o
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ccflags-y += -I$(srctree)/drivers/cxl
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CFLAGS_trace.o = -DTRACE_INCLUDE_PATH=. -I$(src)
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cxl_core-y := port.o
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cxl_core-y += pmem.o
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cxl_core-y += regs.o
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cxl_core-y += memdev.o
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cxl_core-y += mbox.o
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cxl_core-y += pci.o
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cxl_core-y += hdm.o
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cxl_core-y += pmu.o
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cxl_core-y += cdat.o
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cxl_core-y += ras.o
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cxl_core-y += acpi.o
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cxl_core-$(CONFIG_TRACING) += trace.o
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cxl_core-$(CONFIG_CXL_REGION) += region.o
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cxl_core-$(CONFIG_CXL_MCE) += mce.o
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cxl_core-$(CONFIG_CXL_FEATURES) += features.o
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